AD7711A Analog Devices, AD7711A Datasheet - Page 16

• Manufacturer Part Number: AD7711A
• Description: CMOS, 24-Bit Sigma-Delta, Signal Conditioning ADC with RTD Current Source
• Manufacturer: Analog Devices

Specifications of AD7711A

• Resolution (bits): 24bit
• # Chan: 2
• Sample Rate: 19.5kSPS
• Interface: Ser
• Analog Input Type: Diff-Bip,Diff-Uni
• Ain Range: Bip (Vref)/(PGA Gain),Uni (Vref)/(PGA Gain)
• Adc Architecture: Sigma-Delta
• Pkg Type: DIP,SOIC

AD7711A
Bipolar/Unipolar Inputs
The two analog inputs on the AD7711A can accept either uni-
polar or bipolar input voltage ranges. Bipolar or unipolar
options are chosen by programming the B/U bit of the control
register. This programs both channels for either unipolar or
bipolar operation. Programming the part for either unipolar or
bipolar operation does not change any of the input signal condi-
tioning; it simply changes the data output coding. The data coding
is binary for unipolar inputs and offset binary for bipolar inputs.
The input channels are differential and, as a result, the voltage
to which the unipolar and bipolar signals are referenced is the
voltage on the AIN(–) input. For example, if AIN(–) is +1.25 V
and the AD7711A is configured for unipolar operation with a
gain of 1 and a V
AIN(+) input is 1.25 V to 3.75 V. If AIN(–) is 1.25 V and the
AD7711A is configured for bipolar mode with a gain of 1 and
a V
–1.25 V to +3.75 V.
REFERENCE INPUT/OUTPUT
The AD7711A contains a temperature compensated 2.5 V
reference, which has an initial tolerance of ± 1%. This reference
voltage is provided at the REF OUT pin and can be used as the
reference voltage for the part by connecting the REF OUT pin
to the REF IN(+) pin. This REF OUT pin is a single-ended
output, referenced to AGND, that is capable of providing up to
1 mA to an external load. In applications where REF OUT is
connected to REF IN(+), REF IN(–) should be tied to AGND
to provide the nominal 2.5 V reference for the AD7711A.
The reference inputs of the AD7711A, REF IN(+) and REF
IN(–), provide a differential reference input capability. The
common-mode range for these differential inputs is from V
AV
REF IN(–)), is 2.5 V for specified operation, but the reference
voltage can go to 5 V with no degradation in performance provided
that the absolute value of REF IN(+) and REF IN(–) does not
exceed its AV
limits are obeyed. The part is also functional with V
down to 1 V but with degraded performance as the output noise
will, in terms of LSB size, be larger. REF IN(+) must always be
greater than REF IN(–) for correct operation of the AD7711A.
Both reference inputs provide a high impedance, dynamic load
similar to the analog inputs. The maximum dc input leakage
current is 10 pA (± 1 nA over temperature), and source resis-
tance may result in gain errors on the part. The reference inputs
look like the analog input (see Figure 7). In this case, R
5 kW typ and C
f
C
5 pF; for a gain of 64, it is 2.5 pF; and for a gain of 128, it is
1.25 pF.
The digital filter of the AD7711A removes noise from the refer-
ence input just as it does with the analog input, and the same
limitations apply regarding lack of noise rejection at integer
multiples of the sampling frequency. The output noise perfor-
mance outlined in Tables I and II assumes a clean reference.
CLK IN
INT
DD
REF
is 20 pF; for a gain of 16, it is 10 pF; for a gain of 32, it is
. The nominal differential voltage, V
/256 and does not vary with gain. For gains of 1 to 8,
of 2.5 V, the analog input range on the AIN(+) input is
DD
INT
and V
REF
varies with gain. The input sample rate is
of 2.5 V, the input voltage range on the
SS
limits and the V
BIAS
REF
input voltage range
(REF IN(+) –
REF
voltages
INT
SS
is
to
–16–
If the reference noise in the bandwidth of interest is excessive, it
can degrade the performance of the AD7711A. Using the on-
chip reference as the reference source for the part (i.e., connect-
ing REF OUT to REF IN) results in somewhat degraded output
noise performance from the AD7711A for portions of the noise
table that are dominated by the device noise. The on-chip
reference noise effect is eliminated in ratiometric applications
where the reference is used to provide the excitation voltage for
the analog front end. The connection scheme shown in Figure 8
is recommended when using the on-chip reference. Recom-
mended reference voltage sources for the AD7711A include the
AD780 and AD680 2.5 V references.
V
The V
circuitry is biased. It essentially provides the return path for
analog currents flowing in the modulator and, as such, it should
be driven from a low impedance point to minimize errors.
For maximum internal headroom, the V
set halfway between AV
AV
headroom the circuit has at the upper end, while the difference
between V
of headroom the circuit has at the lower end. Care should be
taken in choosing a V
prescribed limits. For single +5 V operation, the selected V
voltage must ensure that V
AV
+ 2.1 V and less than AV
or dual ± 5 V operation, the selected V
that V
the V
AV
and V
2.125 V to 2.625 V. With AV
5 V, the range for V
+4.75 V, V
is –2.625 V to +2.625 V.
The V
ply rejection performance of the AD7711A. If the V
tracks the AV
from the AV
external Zener diode connected between the AV
V
in AV
BIAS
BIAS
DD
DD
DD
BIAS
as the source for the V
DD
Input
REF
BIAS
BIAS
BIAS
and (V
or V
–3 V. For example, with AV
power supply rejection performance.
voltage itself is greater than V
= 2.5 V, the allowable range for the V
SS
± 0.85 ¥ V
input determine at what voltage the internal analog
voltage does have an effect on the AV
SS
SS
Figure 8. REF OUT/REF IN Connection
and (V
DD
BIAS
or that the V
= –4.75 V, and V
DD
supply line from 80 dB to 95 dB. Using an
supply, it improves the power supply rejection
+ 0.85 ¥ V
BIAS
BIAS
REF
BIAS
AD7711A
REF OUT
DD
– 0.85 ¥ V
is 4.25 V to 5.25 V. With AV
does not exceed AV
DD
voltage to ensure that it stays within
BIAS
BIAS
and V
BIAS
REF
– 2.1 V. For single +10 V operation
DD
voltage itself is greater than V
± 0.85 ¥ V
REF
) determines the amount of
REF IN(+)
= 9.5 V, V
voltage gives the improvement
REF IN(–)
SS
DD
REF
. The difference between
= +2.5 V, the V
) determines the amount
= 4.75 V, V
BIAS
SS
BIAS
+ 3 V or less than
REF
voltage must ensure
SS
voltage should be
DD
does not exceed
= 0 V and V
BIAS
or V
DD
DD
SS
BIAS
power sup-
line and
voltage is
BIAS
= 0 V
SS
DD
range
or that
voltage
REV. D
=
REF
BIAS
SS
=