AD7711A Analog Devices, AD7711A Datasheet - Page 22

• Manufacturer Part Number: AD7711A
• Description: CMOS, 24-Bit Sigma-Delta, Signal Conditioning ADC with RTD Current Source
• Manufacturer: Analog Devices

Specifications of AD7711A

• Resolution (bits): 24bit
• # Chan: 2
• Sample Rate: 19.5kSPS
• Interface: Ser
• Analog Input Type: Diff-Bip,Diff-Uni
• Ain Range: Bip (Vref)/(PGA Gain),Uni (Vref)/(PGA Gain)
• Adc Architecture: Sigma-Delta
• Pkg Type: DIP,SOIC

AD7711A
Figures 12a and 12b show timing diagrams for reading from the
AD7711A in the external clocking mode. Figure 12a shows a
situation where all the data is read from the AD7711A in one
read operation. Figure 12b shows a situation where the data is
read from the AD7711A over a number of read operations. Both
read operations show a read from the AD7711A’s output data
register. Reads from the control register and calibration registers
are similar but, in these cases, the DRDY line is not related to
the read function. Depending on the output update rate, it can
go low at any stage in the control/calibration register read cycle
without affecting the read, and its status should be ignored. A
read operation from either the control or calibration registers
must always read 24 bits of data from the respective register.
Figure 12a shows a read operation from the AD7711A where
RFS remains low for the duration of the data word transmission.
With DRDY low, the RFS input is brought low. The input
SCLK signal should be low between read and write operations.
RFS going low places the MSB of the word to be read on the
serial data line. All subsequent data bits are clocked out on a
high to low transition of the serial clock and are valid prior to
the following rising edge of this clock. The penultimate falling
Figure 12b. External Clocking Mode, Output Data Read Operation ( RFS Returns High during Read Operation)
SDATA (O)
SDATA (O)
DRDY (O)
DRDY (O)
SCLK (I)
SCLK (I)
RFS (I)
RFS (I)
A0 (I)
A0 (I)
Figure 12a. External Clocking Mode, Output Data Read Operation
t
t
20
22
t
20
t
22
t
t
24
24
t
MSB
26
MSB
t
25
t
25
–22–
t
27
edge of SCLK clocks out the LSB and the final falling edge
resets the DRDY line high. This rising edge of DRDY turns off
the serial data output.
Figure 12b shows a timing diagram for a read operation where
RFS returns high during the transmission of the word and
returns low again to access the rest of the data word. Timing
parameters and functions are very similar to that outlined for
Figure 12a, but Figure 12b has a number of additional times to
show timing relationships when RFS returns high in the middle
of transferring a word.
RFS should return high during a low time of SCLK. On the
rising edge of RFS, the SDATA output is turned off. DRDY
remains low and will remain low until all bits of the data-word
are read from the AD7711A, regardless of the number of times
RFS changes state during the read operation. Depending on the
time between the falling edge of SCLK and the rising edge of
RFS, the next bit (BIT N+1) may appear on the data bus before
RFS goes high. When RFS returns low again, it activates the
SDATA output. When the entire word is transmitted, the
DRDY line will go high, turning off the SDATA output as per
Figure 12a.
BIT N
t
26
THREE-STATE
t
t
27
30
t
31
LSB
t
24
t
29
t
21
BIT N+1
t
28
THREE-STATE
t
23
t
25
REV. D