AD7711A Analog Devices, AD7711A Datasheet - Page 19

• Manufacturer Part Number: AD7711A
• Description: CMOS, 24-Bit Sigma-Delta, Signal Conditioning ADC with RTD Current Source
• Manufacturer: Analog Devices

Specifications of AD7711A

• Resolution (bits): 24bit
• # Chan: 2
• Sample Rate: 19.5kSPS
• Interface: Ser
• Analog Input Type: Diff-Bip,Diff-Uni
• Ain Range: Bip (Vref)/(PGA Gain),Uni (Vref)/(PGA Gain)
• Adc Architecture: Sigma-Delta
• Pkg Type: DIP,SOIC

Cal Type
Self-Cal
System Cal
System Cal
System Offset Cal
Background Cal
In the bipolar mode, the system offset calibration range is again
restricted by the span range. The span range of the converter in
bipolar mode is equidistant around the voltage used for the zero-
scale point, thus the offset range plus half the span range cannot
exceed (1.05 ¥ V
the offset span cannot move more than ± (0.05 ¥ V
before the endpoints of the transfer function exceed the input
overrange limits ± (1.05 ¥ V
to the minimum ± (0.4 ¥ V
offset range is ± (0.65
POWER-UP AND CALIBRATION
On power-up, the AD7711A performs an internal reset, which
sets the contents of the control register to a known state. How-
ever, to ensure correct calibration for the device, a calibration
routine should be performed after power-up.
The power dissipation and temperature drift of the AD7711A
are low and no warm-up time is required before the initial cali-
bration is performed. However, if an external reference is being
used, this reference must have stabilized before calibration is
initiated.
Drift Considerations
The AD7711A uses chopper stabilization techniques to mini-
mize input offset drift. Charge injection in the analog switches
and dc leakage currents at the sampling node are the primary
sources of offset voltage drift in the converter. The dc input
leakage current is essentially independent of the selected gain.
Gain drift within the converter depends primarily upon the
temperature tracking of the internal capacitors. It is not affected
by leakage currents.
Measurement errors due to offset drift or gain drift can be elimi-
nated at any time by recalibrating the converter or by operating
the part in the background calibration mode. Using the system
calibration mode can also minimize offset and gain errors in the
signal conditioning circuitry. Integral and differential linearity
errors are not significantly affected by temperature changes.
POWER SUPPLIES AND GROUNDING
Since the analog inputs and reference input are differential,
most of the voltages in the analog modulator are common-mode
voltages. V
currents flowing in the analog modulator. As a result, the V
input should be driven from a low impedance to minimize errors
due to charging/discharging impedances on this line. When the
internal reference is used as the reference source for the part,
AGND is the ground return for this reference voltage.
REV. D
BIAS
provides the return path for most of the analog
REF
/GAIN). If the span is set to 2 ¥ V
¥ V
MD2, MD1, MD0
0, 0, 1
0, 1, 0
0, 1, 1
1, 0, 0
1, 0, 1
REF
REF
REF
/GAIN).
/GAIN), the maximum
/GAIN). If the span range is set
Table VI. Calibration Truth Table
Zero-Scale Cal
Shorted Inputs
AIN
–
AIN
Shorted Inputs
REF
REF
allowable
/GAIN)
/GAIN,
BIAS
–19–
The analog and digital supplies to the AD7711A are indepen-
dent and separately pinned out to minimize coupling between
the analog and digital sections of the device. The digital filter
will provide rejection of broadband noise on the power supplies,
except at integer multiples of the modulator sampling frequency.
The digital supply (DV
supply (AV
rate analog and digital supplies are used, the decoupling scheme
shown in Figure 9 is recommended. In systems where AV
5 V and DV
are driven from the same 5 V supply, although each supply
should be decoupled separately as shown in Figure 9. It is pref-
erable that the common supply is the system’s analog 5 V supply.
It is also important that power is applied to the AD7711A before
signals at REF IN, AIN, or the logic input pins in order to avoid
excessive current. If separate supplies are used for the AD7711A
and the system digital circuitry, then the AD7711A should be
powered up first. If it is not possible to guarantee this, then
current limiting resistors should be placed in series with the
logic inputs.
Full-Scale Cal
V
–
AIN
V
V
REF
REF
REF
Figure 9. Recommended Decoupling Scheme
ANALOG
SUPPLY
10 F
DD
DD
) by more than 0.3 V in normal operation. If sepa-
= 5 V, it is recommended that AV
0.1 F
DD
) must not exceed the analog positive
Sequence
One-Step
Two-Step
Two-Step
One-Step
One-Step
AV
AD7711A
DD
DV
DD
0.1 F
Duration
9 ¥ 1/Output Rate
4 ¥ 1/Output Rate
4 ¥ 1/Output Rate
9 ¥ 1/Output Rate
6 ¥ 1/Output Rate
DIGITAL +5V
AD7711A
SUPPLY
DD
and DV
DD
DD
=
2