AD7711A Analog Devices, AD7711A Datasheet - Page 10

• Manufacturer Part Number: AD7711A
• Description: CMOS, 24-Bit Sigma-Delta, Signal Conditioning ADC with RTD Current Source
• Manufacturer: Analog Devices

Specifications of AD7711A

• Resolution (bits): 24bit
• # Chan: 2
• Sample Rate: 19.5kSPS
• Interface: Ser
• Analog Input Type: Diff-Bip,Diff-Uni
• Ain Range: Bip (Vref)/(PGA Gain),Uni (Vref)/(PGA Gain)
• Adc Architecture: Sigma-Delta
• Pkg Type: DIP,SOIC

AD7711A
PGA GAIN
G2
0
0
0
0
1
1
1
1
Channel Selection
CH
0
1
Power-Down
PD
0
1
Word Length
WL
0
1
RTD Excitation Current
IO
0
1
Burnout Current
BO
0
1
Bipolar/Unipolar Selection (Both Inputs)
B/U
0
1
Filter Selection (FS11–FS0)
The on-chip digital filter provides a sinc
response. The 12 bits of data programmed into these bits deter-
mine the filter cutoff frequency, the position of the first notch of
the filter, and the data rate for the part. In association with the
gain selection, it also determines the output noise (and therefore
the effective resolution) of the device.
The first notch of the filter occurs at a frequency determined by
the relationship filter first notch frequency = (f
where code is the decimal equivalent of the code in bits FS0 to
FS11 and is in the range 19 to 2,000. With the nominal f
of 10 MHz, this results in a first notch frequency range from
9.76 Hz to 1.028 kHz. To ensure correct operation of the
AD7711A, the value of the code loaded to these bits must be
within this range. Failure to do this will result in unspecified
operation of the device.
Changing the filter notch frequency, as well as the selected gain,
impacts resolution. Tables I and II and Figure 2 show the effect
of the filter notch frequency and gain on the effective resolution
of the AD7711A. The output data rate (or effective conversion
Gl
0
0
1
1
0
0
1
1
Channel
AIN1
AIN2
Normal Operation
Power-Down
Output Word Length
16-Bit
24-Bit
Off
On
Off
On
Bipolar
Unipolar
G0
0
1
0
1
0
1
0
1
3
(or (sinx/x)
CLK IN
(Default Condition after the Internal Power-On Reset)
(Default Condition after the Internal Power-On Reset)
(Default Condition after Internal Power-On Reset)
(Default Condition after Internal Power-On Reset)
(Default Condition after Internal Power-On Reset)
(Default Condition after Internal Power-On Reset)
/512)/code
3
) filter
Gain
1
2
4
8
16
32
64
128
CLK IN
–10–
time) for the device is equal to the frequency selected for the
first notch of the filter. For example, if the first notch of the
filter is selected at 50 Hz, then a new word is available at a 50 Hz
rate or every 20 ms. If the first notch is at 1 kHz, a new word is
available every 1 ms.
The settling time of the filter to a full-scale step input change is
worst case 4 ¥ 1/(output data rate). This settling time is to
100% of the final value. For example, with the first filter notch
at 50 Hz, the settling time of the filter to a full-scale step input
change is 80 ms max. If the first notch is at 1 kHz, the settling
time of the filter to a full-scale input step is 4 ms max. This
settling time can be reduced to 3 ¥ l/(output data rate) by syn-
chronizing the step input change to a reset of the digital filter. In
other words, if the step input takes place with SYNC low, the
settling time will be 3 ¥ l/(output data rate). If a change of chan-
nels takes place, the settling time is 3 ¥ l/(output data rate),
regardless of the SYNC input.
The –3 dB frequency is determined by the programmed first
notch frequency according to the relationship filter –3 dB
frequency = 0.262 ¥ first notch frequency.
(Default Condition after the Internal Power-On Reset)
REV. D