AD7711A Analog Devices, AD7711A Datasheet - Page 14

• Manufacturer Part Number: AD7711A
• Description: CMOS, 24-Bit Sigma-Delta, Signal Conditioning ADC with RTD Current Source
• Manufacturer: Analog Devices

Specifications of AD7711A

• Resolution (bits): 24bit
• # Chan: 2
• Sample Rate: 19.5kSPS
• Interface: Ser
• Analog Input Type: Diff-Bip,Diff-Uni
• Ain Range: Bip (Vref)/(PGA Gain),Uni (Vref)/(PGA Gain)
• Adc Architecture: Sigma-Delta
• Pkg Type: DIP,SOIC

AD7711A
Input Sample Rate
The modulator sample frequency for the device remains at
f
selected gain. However, gains greater than ¥1 are achieved by a
combination of multiple input samples per modulator cycle and
scaling the ratio of reference capacitor to input capacitor. As a
result of the multiple sampling, the input sample rate of the device
varies with the selected gain (see Table III). The effective input
impedance is 1/C ¥ f
and f
Gain
1
2
4
8
16
32
64
128
DIGITAL FILTERING
The AD7711A’s digital filter behaves like a similar analog filter,
with a few minor differences.
First, since digital filtering occurs after the A-to-D conversion
process, it can remove noise injected during the conversion
process. Analog filtering cannot do this.
On the other hand, analog filtering can remove noise superim-
posed on the analog signal before it reaches the ADC. Digital
filtering cannot do this, and noise peaks riding on signals near
full scale have the potential to saturate the analog modulator
and digital filter, even though the average value of the signal is
within limits. To alleviate this problem, the AD7711A has
overrange headroom built into the sigma-delta modulator and
digital filter, which allows overrange excursions of 5% above the
analog input range. If noise signals are larger than this, consid-
eration should be given to analog input filtering, or to reducing
the input channel voltage so that its full scale is half that of the
analog input channel full scale. This will provide an overrange
capability greater than 100% at the expense of reducing the
dynamic range by 1 bit (50%).
Filter Characteristics
The cutoff frequency of the digital filter is determined by the
value loaded to bits FS0 to FS11 in the control register. At the
maximum clock frequency of 10 MHz, the minimum cutoff
frequency of the filter is 2.58 Hz while the maximum program-
mable cutoff frequency is 269 Hz.
Figure 6 shows the filter frequency response for a cutoff fre-
quency of 2.62 Hz, which corresponds to a first filter notch
frequency of 10 Hz. This is a (sinx/x)
sinc
Programming a different cutoff frequency via FS0–FS11 does
not alter the profile of the filter response; it changes the fre-
quency of the notches as outlined in the Control Register section.
CLK IN
3
) that provides >100 dB of 50 Hz and 60 Hz rejection.
S
/512 (19.5 kHz @ f
is the input sample rate.
Table III. Input Sampling Frequency vs. Gain
f
2 ¥ f
4 ¥ f
8 ¥ f
8 ¥ f
8 ¥ f
8 ¥ f
8 ¥ f
Input Sampling Frequency (f
CLK IN
S
where C is the input sampling capacitance
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
/256 (39 kHz @ f
CLK IN
/256 (78 kHz @ f
/256 (156 kHz @ f
/256 (312 kHz @ f
/256 (312 kHz @ f
/256 (312 kHz @ f
/256 (312 kHz @ f
/256 (312 kHz @ f
= 10 MHz) regardless of the
3
response (also called
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
= 10 MHz)
S
)
= 10 MHz)
= 10 MHz)
= 10 MHz)
= 10 MHz)
= 10 MHz)
= 10 MHz)
= 10 MHz)
–14–
Since the AD7711A contains this on-chip, low-pass filtering,
there is a settling time associated with step function inputs, and
data on the output will be invalid after a step change until the
settling time has elapsed. The settling time depends upon the
notch frequency chosen for the filter. The output data rate
equates to this filter notch frequency, and the settling time of
the filter to a full-scale step input is four times the output data
period. In applications using both input channels, the settling
time of the filter must be allowed to elapse before data from the
second channel is accessed.
Post Filtering
The on-chip modulator provides samples at a 19.5 kHz output
rate. The on-chip digital filter decimates these samples to pro-
vide data at an output rate that corresponds to the programmed
first notch frequency of the filter. Since the output data rate
exceeds the Nyquist criterion, the output rate for a given band-
width will satisfy most application requirements. However, there
may be some applications that require a higher data rate for a
given bandwidth and noise performance. Applications that need
this higher data rate will require some post filtering following
the digital filter of the AD7711A.
For example, if the required bandwidth is 7.86 Hz but the
required update rate is 100 Hz, the data can be taken from the
AD7711A at the 100 Hz rate giving, a –3 dB bandwidth of
26.2 Hz. Post filtering can be applied to this to reduce the band-
width and output noise, to the 7.86 Hz bandwidth level, while
maintaining an output rate of 100 Hz.
Post filtering can also be used to reduce the output noise from
the device for bandwidths below 2.62 Hz. At a gain of 128, the
output rms noise is 250 nV. This is essentially device noise or
white noise, and since the input is chopped, the noise has a flat
frequency response. By reducing the bandwidth below 2.62 Hz,
the noise in the resultant passband can be reduced. A reduction
in bandwidth by a factor of 2 results in a ÷2 reduction in the
output rms noise. This additional filtering will result in a longer
settling time.
Figure 6. Frequency Response of AD7711A Filter
–100
–120
–140
–160
–180
–200
–220
–240
–20
–40
–60
–80
0
0
10
20
FREQUENCY (Hz)
30
40
50
60
70
REV. D