AD7711A Analog Devices, AD7711A Datasheet - Page 12

• Manufacturer Part Number: AD7711A
• Description: CMOS, 24-Bit Sigma-Delta, Signal Conditioning ADC with RTD Current Source
• Manufacturer: Analog Devices

Specifications of AD7711A

• Resolution (bits): 24bit
• # Chan: 2
• Sample Rate: 19.5kSPS
• Interface: Ser
• Analog Input Type: Diff-Bip,Diff-Uni
• Ain Range: Bip (Vref)/(PGA Gain),Uni (Vref)/(PGA Gain)
• Adc Architecture: Sigma-Delta
• Pkg Type: DIP,SOIC

AD7711A
CIRCUIT DESCRIPTION
The AD7711A is a sigma-delta A/D converter with on-chip
digital filtering, intended for the measurement of wide dynamic
range, low frequency signals such as those in weigh scale, indus-
trial control, or process control applications. It contains a sigma-
delta (or charge balancing) ADC, a calibration microcontroller
with on-chip static RAM, a clock oscillator, a digital filter, and a
bidirectional serial communications port.
The part contains two programmable gain differential analog
input channels. The gain range is from 1 to 128, allowing the
part to accept unipolar signals of between 0 mV and 20 mV and
0 V and 2.5 V or bipolar signals in the range from ± 20 mV to
± 2.5 V when the reference input voltage equals 2.5 V. The
input signal to the selected analog input channel is continu-
ously sampled at a rate determined by the frequency of the
master clock, MCLK IN, and the selected gain (see Table
III). A charge-balancing A/D converter (sigma-delta modulator)
converts the sampled signal into a digital pulse train whose duty
cycle contains the digital information. The programmable gain
function on the analog input is also incorporated in this sigma-
delta modulator with the input sampling frequency being modi-
fied to give the higher gains. A sinc
processes the output of the sigma-delta modulator and updates
the output register at a rate determined by the first notch fre-
quency of this filter. The output data can be read from the serial
port randomly or periodically at any rate up to the output regis-
ter update rate. The first notch of this digital filter (and there-
fore its –3 dB frequency) can be programmed via an on-chip
control register. The programmable range for this first notch
frequency is from 9.76 Hz to 1.028 kHz, giving a programmable
range for the –3 dB frequency of 2.58 Hz to 269 Hz.
Figures 2a and 2b give information similar to that outlined in Table I. In these plots, the output rms noise is shown for the full
range of available cutoffs frequencies rather than for some typical cutoff frequencies as in Tables I and II. The numbers given in
these plots are typical values at 25∞C.
10000
Figure 2a. Plot of Output Noise vs. Gain and Notch
Frequency (Gains of 1 to 8)
1000
100
0.1
10
1
10
NOTCH FREQUENCY – Hz
100
3
digital low-pass filter
1000
GAIN OF 1
GAIN OF 2
GAIN OF 4
GAIN OF 8
10000
–12–
The basic connection diagram for the part is shown in Figure 3.
This shows the AD7711A in the external clocking mode with
both the AV
from the analog 5 V supply. Some applications will have
separate supplies for both AV
these cases, the analog supply will exceed the 5 V digital supply
(see the Power Supplies and Grounding section).
ANALOG GROUND
DIGITAL GROUND
5V SUPPLY
ANALOG
Figure 2b. Plot of Output Noise vs. Gain and Notch
Frequency (Gains of 16 to 128)
10000
ANALOG INPUT
ANALOG INPUT
1000
DIFFERENTIAL
DIFFERENTIAL
100
0.1
10
1
10
DD
Figure 3. Basic Connection Diagram
10 F
and DV
0.1 F
DD
NOTCH FREQUENCY – Hz
AIN1(+)
AIN1(–)
AIN2(+)
AIN2(–)
RTD CURRENT
AGND
V
DGND
REF OUT
REF IN(+)
V
REF IN(–)
100
SS
BIAS
pins of the AD7711A being driven
DD
AV
AD7711A
DD
and DV
DV
MCLK OUT
DD
MCLK IN
SDATA
MODE
1000
DRDY
SCLK
SYNC
DD
RFS
TFS
A0
GAIN OF 16
GAIN OF 32
GAIN OF 64
GAIN OF 128
, and in some of
0.1 F
5V
DATA READY
TRANSIT (WRITE)
RECEIVE (READ)
SERIAL DATA
SERIAL CLOCK
ADDRESS INPUT
10000
REV. D