AD7711A Analog Devices, AD7711A Datasheet
AD7711A
Specifications of AD7711A
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AD7711A Summary of contents
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... RTD current control, and calibration modes. 4. The AD7711A allows the user to read and to write the on-chip calibration registers. This means that the micro- controller has much greater control over the calibration procedure ...
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... AD7711A–SPECIFICATIONS REF IN(–) = AGND; MCLK MHz, unless otherwise stated. All specifications T Parameter STATIC PERFORMANCE No Missing Codes Output Noise Integral Nonlinearity @ 25∞ MIN MAX Positive Full-Scale Error 5 Full-Scale Drift 2, 4 Unipolar Offset Error 5 Unipolar Offset Drift 2, 4 Bipolar Zero Error ...
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... Output Compliance SYSTEM CALIBRATION 14 Positive Full-Scale Calibration Limit 14 Negative Full-Scale Calibration Limit 15 Offset Calibration Limit 15 Input Span NOTES 12 The AD7711A is tested with the following V BIAS and V = – BIAS 13 Guaranteed by design, not production tested. 14 After calibration, if the analog input exceeds positive full scale, the converter will output all 1s. If the analog input is less than negative full scale, then the device will output all 0s ...
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... Power Dissipation Normal Mode Normal Mode Standby (Power-Down) Mode NOTES 16 The AD7711A is specified with a 10 MHz clock for AV than 10.5 V. Operating with AV voltages in the range 5. 10 guaranteed only over the temperature range. DD The ± 5% tolerance on the DV 17 input is allowed provided that DV ...
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... The AD7711A is specified with a 10 MHz clock for AV than 10 CLK IN duty cycle range is 45% to 55%. CLK IN must be supplied whenever the AD7711A is not in STANDBY mode clock is present in this case, the device can draw higher current than specified and possibly become uncalibrated. 5 ...
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... DIP and SOIC SCLK 1 24 DGND MCLK SDATA MCLK OUT 3 22 DRDY RFS SYNC 5 20 AD7711A TFS MODE 6 19 TOP VIEW (Not to Scale) AIN1(+) 7 18 AGND RTD CURRENT AIN1(– AIN2(+) REF OUT 9 16 AIN2(–) REF IN(+) 10 ...
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... Address Input. With this input low, reading and writing to the device is to the control register. With this input high, access is to either the data register or the calibration registers. SYNC 5 Logic Input. Allows for synchronization of the digital filters when using a number of AD7711As. It resets the nodes of the digital filter. 6 MODE Logic Input ...
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... AD7711A can accept and still accurately calibrate offset. Full-Scale Calibration Range This is the range of voltages that the AD7711A can accept in the system calibration mode and still correctly calibrate full scale. Input Span In system calibration schemes, two voltages applied in sequence to the AD7711A’ ...
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... Activate Background Calibration. This activates background calibration on the channel selected by CH. If the background calibration mode is on, then the AD7711A provides continuous self-calibration of the reference and shorted (zeroed) inputs. This calibration takes place as part of the conversion sequence, extending the conversion time and reducing the word rate by a factor of 6. Its major advantage is that the user does not have to worry about recalibrating the device when there is a change in the ambient temperature ...
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... FS11 and is in the range 19 to 2,000. With the nominal MHz, this results in a first notch frequency range from 9. 1.028 kHz. To ensure correct operation of the AD7711A, the value of the code loaded to these bits must be within this range. Failure to do this will result in unspecified operation of the device. ...
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... Effective Resolution* (Bits) Gain of Gain of Gain 21 19.5 18.5 18.5 18.5 15 15 –11– AD7711A /GAIN, i.e., the input full REF Gain of Gain of Gain 0.25 0.25 0.25 0.44 0.41 0.38 0.45 0.43 0.4 0.54 0.46 0.46 0.63 0.62 0.6 1.1 0.9 0.65 7.5 4.0 2 180 120 70 Gain of Gain of Gain of 16 ...
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... Figure 2b. Plot of Output Noise vs. Gain and Notch Frequency (Gains 128) The basic connection diagram for the part is shown in Figure 3. This shows the AD7711A in the external clocking mode with both the AV from the analog 5 V supply. Some applications will have separate supplies for both AV these cases, the analog supply will exceed the 5 V digital supply (see the Power Supplies and Grounding section) ...
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... The AD7711A can be operated in single-supply systems pro- vided that the analog input voltage does not go more negative than –30 mV. For larger bipolar signals the part. For battery operation, the AD7711A also offers a software programmable standby mode that reduces idle power consumption typically. ...
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... For example, if the required bandwidth is 7.86 Hz but the required update rate is 100 Hz, the data can be taken from the AD7711A at the 100 Hz rate giving, a –3 dB bandwidth of 26.2 Hz. Post filtering can be applied to this to reduce the band- width and output noise, to the 7.86 Hz bandwidth level, while maintaining an output rate of 100 Hz ...
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... Burnout Current HIGH The AIN1(+) input of the AD7711A contains a 4.5 mA current 1G source that can be turned on/off via the control register. This current source can be used in checking that a transducer has not burned out or gone open circuit before attempting to take mea- surements on that channel ...
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... V of 2.5 V, the input voltage range on the REF AIN(+) input AIN(–) is 1.25 V and the AD7711A is configured for bipolar mode with a gain of 1 and 2.5 V, the analog input range on the AIN(+) input is REF –1. +3.75 V. ...
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... REV. D where the power-on default conditions of the AD7711A are acceptable, and no calibration is performed after power-on, issuing a SYNC pulse to the AD7711A will reset the AD7711A’s digital filter logic the SYNC line, with R, C time constant longer than the DV SYNC function. ...
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... MD1, MD0 of the control register. When invoked, the back- ground calibration mode reduces the output data rate of the AD7711A by a factor of 6 while the –3 dB bandwidth remains unchanged. Its advantage is that the part is continually perform- ing calibration and automatically updating its calibration coeffi- cients ...
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... Figure pref- erable that the common supply is the system’s analog 5 V supply also important that power is applied to the AD7711A before signals at REF IN, AIN, or the logic input pins in order to avoid excessive current. If separate supplies are used for the AD7711A and the system digital circuitry, then the AD7711A should be powered up first ...
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... The AD7711A’s serial communications port provides a flexible arrangement to allow easy interfacing to industry-standard microprocessors, microcontrollers, and digital signal processors. A serial read to the AD7711A can access data from the output register, the control register, or the calibration registers. A serial write to the AD7711A can write data to the control register or the calibration registers ...
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... The serial data to be loaded to the AD7711A must be valid on the rising edge of this SCLK signal. Data is clocked into the AD7711A on the rising edge of the SCLK signal, with the MSB transferred first. On the last active high time of SCLK, the LSB is loaded to the AD7711A. Subsequent to the next falling edge of SCLK, the SCLK output is turned off ...
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... Figures 12a and 12b show timing diagrams for reading from the AD7711A in the external clocking mode. Figure 12a shows a situation where all the data is read from the AD7711A in one read operation. Figure 12b shows a situation where the data is read from the AD7711A over a number of read operations. Both read operations show a read from the AD7711A’ ...
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... SCLK signal. TFS should return high during the low time of SCLK. After TFS returns low again, the next bit of the data-word to be loaded to the AD7711A is clocked in on next high level of the SCLK input. On the last high time of the SCLK input, the LSB is loaded to the AD7711A ...
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... This depends on whether the first bit transmitted by the microprocessor is the MSB or the LSB. The AD7711A expects the MSB as the first bit in the data stream. In cases where the data is being read or being written in bytes and the data has to be reversed, the bits will have to be reversed for every byte. – ...
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... AD7711A. The 8XC51 outputs the LSB first in a write operation while the AD7711A expects the MSB first so the data to be transmitted has to be rearranged before being written to the output serial register. Similarly, the AD7711A outputs the MSB first during a read operation while the 8XC51 expects the LSB first ...
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... The 68HC11 is configured in the master mode with its CPOL bit set to a Logic 0 and its CPHA bit set to a Logic 1. With a 10 MHz master clock on the AD7711A, the interface will oper- ate with all four serial clock rates of the 68HC11. DV ...
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... COMPLIANT TO JEDEC STANDARDS MS-013AD CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN –27– 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20 10.65 (0.4193) 10.00 (0.3937) 0.75 (0.0295) 45 0.25 (0.0098 1.27 (0.0500) 0.40 (0.0157) AD7711A 2 ...
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... AD7711A Revision History Location 2/04—Data Sheet changed from REV REV. D. Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Deleted AD7711 to ADSP-2105 Interface section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Updated AD7711A to 68HC11 Interface section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 –28– Page REV. D ...