SC16C852SVIET,115 NXP Semiconductors, SC16C852SVIET,115 Datasheet - Page 8

• Manufacturer Part Number: SC16C852SVIET,115
• Description: IC UART DL 1.8V W/FIFO 36-TFBGA
• Manufacturer: NXP Semiconductors

Specifications of SC16C852SVIET,115

• Features: Programmable
• Number Of Channels: 2, DUART
• Fifo's: 128 Byte
• Protocol: RS485
• Voltage - Supply: 1.8V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 36-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935286451115; SC16C852SVIET-G; SC16C852SVIET-G

NXP Semiconductors
SC16C852SV_1
Product data sheet
6.2 Extended mode (128-byte FIFO)
6.3 Internal registers
The device is in the extended mode when any of these four registers contains any value
other than 0: FLWCNTH, FLWCNTL, TXINTLVL, RXINTLVL.
The SC16C852SV provides two sets of internal registers (A and B) consisting of
25 registers each for monitoring and controlling the functions of each channel of the
UART. These registers are shown in
Table 4.
A3
General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LSR, SPR)
0
0
0
0
1
1
1
1
Baud rate register set (DLL/DLM)
0
0
Second special register set (TXLVLCNT/RXLVLCNT)
0
1
Enhanced register set (EFR, Xon1/Xon2, Xoff1/Xoff2)
0
1
1
1
1
First extra feature register set (TXINTLVL/RXINTLVL, FLWCNTH/FLWCNTL)
0
1
1
1
Second extra feature register set (CLKPRES, SAMPR, RS485TIME, AFCR2, AFCR1)
0
0
1
1
1
A2
0
0
1
1
0
0
1
1
0
0
1
0
1
0
0
1
1
1
0
1
1
1
1
0
1
1
Internal registers decoding
A1
0
1
0
1
0
1
0
1
0
1
1
0
0
0
1
0
1
0
0
0
1
0
1
0
0
1
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
Read mode
Receive Holding Register
Interrupt Enable Register
Interrupt Status Register
Line Control Register
Modem Control Register
Line Status Register
Modem Status Register
Scratchpad Register
LSB of Divisor Latch
MSB of Divisor Latch
Transmit FIFO Level Count
Receive FIFO Level Count
Enhanced Feature Register
Xon1 word
Xon2 word
Xoff1 word
Xoff2 word
Transmit FIFO Interrupt Level
Receive FIFO Interrupt Level
Flow Control Count High
Flow Control Count Low
Clock Prescaler
Sampling rate
RS-485 turn-around Timer
Additional Feature Control Register 2
Additional Feature Control Register 1
Rev. 01 — 23 September 2008
[2]
Table
4.
[3]
[4]
Write mode
Transmit Holding Register
Interrupt Enable Register
FIFO Control Register
Line Control Register
Modem Control Register
Extra Feature Control Register (EFCR)
n/a
Scratchpad Register
LSB of Divisor Latch
MSB of Divisor Latch
n/a
n/a
Enhanced Feature Register
Xon1 word
Xon2 word
Xoff1 word
Xoff2 word
Transmit FIFO Interrupt Level
Receive FIFO Interrupt Level
Flow Control Count High
Flow Control Count Low
Clock Prescaler
Sampling rate
RS-485 turn-around Timer
Additional Feature Control Register 2
Additional Feature Control Register 1
SC16C852SV
[1]
© NXP B.V. 2008. All rights reserved.
[5]
[6]
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