SC16C852SVIET,115 NXP Semiconductors, SC16C852SVIET,115 Datasheet - Page 31

• Manufacturer Part Number: SC16C852SVIET,115
• Description: IC UART DL 1.8V W/FIFO 36-TFBGA
• Manufacturer: NXP Semiconductors

Specifications of SC16C852SVIET,115

• Features: Programmable
• Number Of Channels: 2, DUART
• Fifo's: 128 Byte
• Protocol: RS485
• Voltage - Supply: 1.8V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 36-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935286451115; SC16C852SVIET-G; SC16C852SVIET-G

NXP Semiconductors
SC16C852SV_1
Product data sheet
7.14 Enhanced Feature Register (EFR)
Enhanced features are enabled or disabled using this register.
Bit 0 through bit 4 provide single or dual character software flow control selection. When
the Xon1 and Xon2 and/or Xoff1 and Xoff2 modes are selected, the double 8-bit words
are concatenated into two sequential numbers.
Table 23.
[1]
Table 24.
Bit
7
6
5
4
3:0
Cont-3
0
1
0
Enhanced function control bits: IER[7:4], ISR[5:4], FCR[5:4] and MCR[7:5].
Symbol
EFR[7]
EFR[6]
EFR[5]
EFR[4]
EFR[3:0] Cont-3:0 Tx, Rx control. Logic 0 or cleared is the default condition. Combinations
Cont-2
0
0
1
Enhanced Feature Register bits description
Software flow control functions
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
Description
Automatic CTS flow control.
Automatic RTS flow control. Automatic RTS may be used for hardware flow
control by enabling EFR[6]. When Auto-RTS is selected, an interrupt will be
generated when the receive FIFO is filled to the programmed trigger level and
RTS will go to a logic 1 at the next trigger level. RTS will return to a logic 0 when
data is unloaded below the next lower trigger level (programmed trigger level 1).
The state of this register bit changes with the status of the hardware flow control.
RTS functions normally when hardware flow control is disabled.
Special Character Detect.
Enhanced function control bit. The content of IER[7:4], ISR[5:4], FCR[5:4], and
MCR[7:5] can be modified and latched. After modifying any bits in the enhanced
registers, EFR[4] can be set to a logic 0 to latch the new values. This feature
prevents existing software from altering or overwriting the SC16C852SV
enhanced functions.
of software flow control can be selected by programming these bits. See
Table
logic 0 = automatic CTS flow control is disabled (normal default condition)
logic 1 = enable automatic CTS flow control. Transmission will stop when CTS
goes to a logical 1. Transmission will resume when the CTS signal returns to a
logical 0.
logic 0 = automatic RTS flow control is disabled (normal default condition)
logic 1 = enable automatic RTS flow control
logic 0 = special character detect disabled (normal default condition)
logic 1 = special character detect enabled. The SC16C852SV compares each
incoming receive character with Xoff2 data. If a match exists, the received data
will be transferred to FIFO and ISR[4] will be set to indicate detection of special
character. Bit-0 in the X-registers corresponds with the LSB bit for the receive
character. When this feature is enabled, the normal software flow control must
be disabled (EFR[3:0] must be set to a logic 0).
logic 0 = disable/latch enhanced features
logic 1 = enables the enhanced functions
enhanced features of the SC16C852SV are enabled and user settings stored
during a reset will be restored.
Cont-1
X
X
X
Rev. 01 — 23 September 2008
24.
Cont-0
X
X
X
TX, RX software flow controls
No transmit flow control
Transmit Xon1/Xoff1
Transmit Xon2/Xoff2
[1]
[1]
[1]
. When this bit is set to a logic 1, all
SC16C852SV
© NXP B.V. 2008. All rights reserved.
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