SC16C852SVIET,115 NXP Semiconductors, SC16C852SVIET,115 Datasheet - Page 16

• Manufacturer Part Number: SC16C852SVIET,115
• Description: IC UART DL 1.8V W/FIFO 36-TFBGA
• Manufacturer: NXP Semiconductors

Specifications of SC16C852SVIET,115

• Features: Programmable
• Number Of Channels: 2, DUART
• Fifo's: 128 Byte
• Protocol: RS485
• Voltage - Supply: 1.8V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 36-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935286451115; SC16C852SVIET-G; SC16C852SVIET-G

NXP Semiconductors
SC16C852SV_1
Product data sheet
6.11.1 Conditions to enter Sleep mode
6.11.2 Conditions to resume normal operation
6.11 Sleep mode
6.12 Low Power feature
Sleep mode is an enhanced feature of the SC16C852SV UART. It is enabled when
EFR[4], the enhanced functions bit, is set and when IER[4] of both channels are set.
Sleep mode is entered when:
In Sleep mode, the UART clock and baud rate clock are stopped. Since most registers are
clocked using these clocks, the power consumption is greatly reduced.
Remark: Writing to the divisor latches, DLL and DLM, to set the baud clock, must not be
done during Sleep mode. Therefore, it is advisable to disable Sleep mode using IER[4]
before writing to DLL or DLM.
SC16C852SV resumes normal operation by any of the following:
If the device is awakened by one of the conditions described above, it will return to the
Sleep mode automatically after all the conditions described in
device will stay in Sleep mode until it is disabled by setting any channel’s IER bit 4 to a
logic 0.
When the SC16C852SV is in Sleep mode and the host interface bus (AD7 to AD0, IOW,
IOR, CS) remains in steady state, either HIGH or LOW, the sleep current will be in the
microampere range as specified in
is toggling or floating then the sleep current will be higher.
A Low Power feature is provided by the SC16C852SV to prevent the switching of the host
data bus from influencing the sleep current. When the pin LOWPWR is activated (logic
HIGH), the device immediately and unconditionally goes into Low Power mode. All clocks
are stopped and most host interface pins are isolated to reduce power consumption. The
device only returns to normal mode when the LOWPWR pin is de-asserted. The pin can
be left unconnected because it has an internal pull-down resistor.
•
•
•
•
•
•
•
•
Modem input pins are not toggling.
The serial data input line, RXA/RXB, is idle for 4 character time (logic HIGH) and
AFCR1[4] is 0. When AFCR1[4] is 1, the device will go to sleep regardless of the state
of the RXA/RXB pin (see
The TX FIFO and TX shift register are empty.
There are no interrupts pending.
The RX FIFO is empty.
Receives a start bit on RXA or RXB pin.
Data is loaded into transmit FIFO.
A change of state on any of the modem input pins.
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
Rev. 01 — 23 September 2008
Section 7.22
Table 37 “Static
for the description of AFCR1 bit 4).
characteristics”. If any of these signals
SC16C852SV
Section 6.11.1
© NXP B.V. 2008. All rights reserved.
are met. The
16 of 48