SC16C852SVIET,115 NXP Semiconductors, SC16C852SVIET,115 Datasheet - Page 27

IC UART DL 1.8V W/FIFO 36-TFBGA

SC16C852SVIET,115

Manufacturer Part Number
SC16C852SVIET,115
Description
IC UART DL 1.8V W/FIFO 36-TFBGA
Manufacturer
NXP Semiconductors
Datasheet

Specifications of SC16C852SVIET,115

Features
Programmable
Number Of Channels
2, DUART
Fifo's
128 Byte
Protocol
RS485
Voltage - Supply
1.8V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Package / Case
36-TFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935286451115
SC16C852SVIET-G
SC16C852SVIET-G

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SC16C852SVIET,115
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
SC16C852SV_1
Product data sheet
7.6 Modem Control Register (MCR)
This register controls the interface with the modem or a peripheral device.
Table 18.
Table 19.
Bit
7
6
5
4
3
2
1
0
MCR[3]
0
1
Symbol Description
MCR[7] Clock select
MCR[6] IR enable (see
MCR[5] Reserved; set to ‘0’.
MCR[4] Loopback. Enable the local Loopback mode (diagnostics). In this mode the
MCR[3] OP2A/OP2B, INT enable
MCR[2] This bit is used in the Loopback mode only. In the Loopback mode, this bit is used
MCR[1] RTS
MCR[0] DTR
Modem Control Register bits description
Interrupt output control
transmitter output (TX) and the receiver input (RX), CTS, DSR, CD, and RI are
disconnected from the SC16C852SV I/O pins. Internally the modem data and
control pins are connected into a loopback data configuration (see
this mode, the receiver and transmitter interrupts remain fully operational. The
Modem Control Interrupts are also operational, but the interrupts’ sources are
switched to the lower four bits of the Modem Control. Interrupts continue to be
controlled by the IER register.
In Loopback mode, this bit is used to write the state of the modem CD interface
signal.
to write the state of the modem RI interface signal.
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
logic 0 = divide-by-1 clock input
logic 1 = divide-by-4 clock input
logic 0 = enable the standard modem receive and transmit input/output interface
(normal default condition)
logic 1 = enable infrared IrDA receive and transmit inputs/outputs. While in this
mode, the TX/RX output/inputs are routed to the infrared encoder/decoder. The
data input and output levels will conform to the IrDA infrared interface
requirement. As such, while in this mode, the infrared TX output will be a logic 0
during idle data conditions.
logic 0 = disable Loopback mode (normal default condition)
logic 1 = enable local Loopback mode (diagnostics)
logic 0 = forces INT (A, B) outputs to the 3-state mode (normal default condition)
logic 1 = forces the INT (A, B) outputs to the active mode
logic 0 = force RTS output to a logic 1 (normal default condition)
logic 1 = force RTS output to a logic 0
logic 0 = force DTR output to a logic 1 (normal default condition)
logic 1 = force DTR output to a logic 0
Rev. 01 — 23 September 2008
INT (A, B) output
3-state
active
Figure
15).
SC16C852SV
© NXP B.V. 2008. All rights reserved.
Figure
7). In
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