SC16C852SVIET,115 NXP Semiconductors, SC16C852SVIET,115 Datasheet - Page 23

• Manufacturer Part Number: SC16C852SVIET,115
• Description: IC UART DL 1.8V W/FIFO 36-TFBGA
• Manufacturer: NXP Semiconductors

Specifications of SC16C852SVIET,115

• Features: Programmable
• Number Of Channels: 2, DUART
• Fifo's: 128 Byte
• Protocol: RS485
• Voltage - Supply: 1.8V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 36-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935286451115; SC16C852SVIET-G; SC16C852SVIET-G

NXP Semiconductors
SC16C852SV_1
Product data sheet
7.3.1 FIFO mode
7.3 FIFO Control Register (FCR)
This register is used to enable the FIFOs, clear the FIFOs and set the receive FIFO trigger
levels.
Table 9.
[1]
[2]
Bit
7:6
5:4
3
2
1
0
For 128-byte FIFO mode, refer to
For 128-byte FIFO mode, refer to
Symbol
FCR[7:6]
FCR[5:4]
FCR[3]
FCR[2]
FCR[1]
FCR[0]
FIFO Control Register bits description
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
Description
Receive trigger level in 32-byte FIFO mode.
These bits are used to set the trigger level for receive FIFO interrupt and flow
control. The SC16C852SV will issue a receive ready interrupt when the
number of characters in the receive FIFO reaches the selected trigger level.
Refer to
Transmit trigger level in 32-byte FIFO mode.
These bits are used to set the trigger level for the transmit FIFO interrupt and
flow control. The SC16C852SV will issue a transmit empty interrupt when the
number of characters in FIFO drops below the selected trigger level. Refer to
Table
reserved
XMIT FIFO reset.
RCVR FIFO reset.
FIFO enable.
Rev. 01 — 23 September 2008
logic 0 = no FIFO transmit reset (normal default condition)
logic 1 = clears the contents of the transmit FIFO and resets the FIFO
counter logic. This bit will return to a logic 0 after clearing the FIFO.
logic 0 = no FIFO receive reset (normal default condition)
logic 1 = clears the contents of the receive FIFO and resets the FIFO
counter logic. This bit will return to a logic 0 after clearing the FIFO.
logic 0 = disable the transmit and receive FIFO (normal default condition)
logic 1 = enable the transmit and receive FIFO
11.
Table
Section
Section
10.
7.16,
7.15,
Section
Section
7.17,
7.17,
Section
Section
[1]
[2]
7.18.
7.18.
SC16C852SV
© NXP B.V. 2008. All rights reserved.
23 of 48