SC16C852SVIET,115 NXP Semiconductors, SC16C852SVIET,115 Datasheet
SC16C852SVIET,115
Specifications of SC16C852SVIET,115
SC16C852SVIET-G
SC16C852SVIET-G
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SC16C852SVIET,115 Summary of contents
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SC16C852SV 1.8 V dual UART, 20 Mbit/s (max.) with 128-byte FIFOs, infrared (IrDA), and XScale VLIO bus interface Rev. 01 — 23 September 2008 1. General description The SC16C852SV is a 1.8 V, low power dual channel Universal Asynchronous Receiver ...
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... NXP Semiconductors I Industrial temperature range ( + Software compatible with industry standard SC16C652B I Software selectable baud rate generator I Supports IrDA version 1.0 (up to 115.2 kbit/s) I Standard modem interface or infrared IrDA encoder/decoder interface I Enhanced Sleep mode and low power feature I Modem control functions (CTS, RTS, DSR, DTR, RI, CD) ...
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... NXP Semiconductors 4. Block diagram SC16C852SVIET AD0 to AD7 DATA BUS IOR AND IOW CONTROL RESET LOGIC LLA REGISTER CS SELECT LOGIC POWER DOWN LOWPWR CONTROL INTERRUPT INTA, INTB CONTROL LOGIC Fig 1. Block diagram of SC16C852SV SC16C852SV_1 Product data sheet Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 2. Fig 3. 5.2 Pin description Table 2. Symbol AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 CDA CDB SC16C852SV_1 Product data sheet Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface ball A1 index area ...
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... NXP Semiconductors Table 2. Symbol CS CTSA CTSB DSRA DSRB DTRA DTRB INTA INTB IOR IOW LLA LOWPWR F1 SC16C852SV_1 Product data sheet Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface Pin description …continued Pin Type Description E2 I Chip Select (active LOW). This pin enables the data transfers between the host and the SC16C852SV for the addressed channel ...
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... NXP Semiconductors Table 2. Symbol RESET RIA RIB RTSA RTSB RXA RXB TXA TXB XTAL1 XTAL2 SC16C852SV_1 Product data sheet Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface Pin description …continued Pin Type Description B5 I Master reset (active LOW). A reset pulse will reset the internal registers and all the outputs ...
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... NXP Semiconductors 6. Functional description The SC16C852SV provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-parallel data conversions for both the transmitter and receiver sections. These functions are necessary for converting the serial data stream into parallel data that is required with digital data systems. Synchronization for the serial data stream is accomplished by adding start and stop bits to the transmit data to form a data character (character orientated protocol) ...
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... NXP Semiconductors 6.2 Extended mode (128-byte FIFO) The device is in the extended mode when any of these four registers contains any value other than 0: FLWCNTH, FLWCNTL, TXINTLVL, RXINTLVL. 6.3 Internal registers The SC16C852SV provides two sets of internal registers (A and B) consisting of 25 registers each for monitoring and controlling the functions of each channel of the UART ...
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... NXP Semiconductors [1] These registers are accessible only when LCR[ logic 0. [2] These registers are accessible only when LCR[ logic 1. [3] Second special register are accessible only when EFCR[ [4] Enhanced feature registers are only accessible when LCR = 0xBF. [5] First extra feature registers are only accessible when EFCR[2:1] = 01b. ...
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... NXP Semiconductors SC16C852SV will suspend TX transmissions as soon as the stop bit of the character in process is shifted out. Transmission is resumed after the CTSx input returns to a logic 0, indicating more data may be sent. When AFCR1[2] is set to 1, then the function of CTSx pin is mapped to the DSRx pin, and the function of RTS is mapped to DTRx pin ...
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... NXP Semiconductors Under the above described flow control mechanisms, flow control characters are not placed (stacked) in the receive FIFO. When using software flow control, the Xon/Xoff characters cannot be used for data transfer. In the event that the receive buffer is overfilling, the SC16C852SV automatically sends an Xoff character (when enabled) via the serial TX output to the remote UART ...
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... NXP Semiconductors 6.9 Programmable baud rate generator The SC16C852SV UART contains a programmable rational baud rate generator that takes any clock input and divides divisor in the range between 1 and (2 SC16C852SV offers the capability of dividing the input frequency by rational divisor. The fractional part of the divisor is controlled by the CLKPRES register in the First Extra Register Set ...
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... NXP Semiconductors However, the user can also select sampling rates (see Rate (SAMPR)”) to operate at four times or two times faster than 16 sampling rate. Programming the baud rate generator registers CLKPRES, DLM (MSB) and DLL (LSB) provides a user capability for selecting the desired final baud rate. The example in shows the selectable baud rate table available when using a 1 ...
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... NXP Semiconductors Table 6. Output baud rate (bit/s) 19.2 k 38.4 k 57.6 k 115.2 k 6.10 Loopback mode The internal loopback capability allows on-board diagnostics. In the Loopback mode, the normal modem interface pins are disconnected and reconfigured for loopback internally (see Figure In the Loopback mode, the transmitter output (TXA/TXB) and the receiver input (RXA/RXB) are disconnected from their associated interface pins, and instead are connected together internally ...
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... NXP Semiconductors SC16C852SV AD0 to AD7 DATA BUS IOR AND IOW CONTROL RESET LOGIC LLA REGISTER CS SELECT LOGIC POWER DOWN LOWPWR CONTROL INTERRUPT INTA, INTB CONTROL LOGIC Fig 7. Internal Loopback mode diagram SC16C852SV_1 Product data sheet Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface ...
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... NXP Semiconductors 6.11 Sleep mode Sleep mode is an enhanced feature of the SC16C852SV UART enabled when EFR[4], the enhanced functions bit, is set and when IER[4] of both channels are set. 6.11.1 Conditions to enter Sleep mode Sleep mode is entered when: • Modem input pins are not toggling. ...
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... NXP Semiconductors 6.13 RS-485 features 6.13.1 Auto RS-485 RTS control Normally the RTSx pin is controlled by MCR bit hardware flow control is enabled, the logic state of the RTSx pin is controlled by the hardware flow control circuitry. EFCR2 register bit 4 will take the precedence over the other two modes; once this bit is set, the transmitter will control the state of the RTSx pin ...
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... NXP Semiconductors 6.13.3.2 Auto address detection If Special Character Detect is enabled (EFR[5] is set and the XOFF2 register contains the address byte), the receiver will try to detect an address byte that matches the programmed character in the XOFF2 register. If the received byte is a data byte or an address byte that does not match the programmed character in the XOFF2 register, the receiver will discard these data ...
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Table 7. SC16C852SV internal registers [ Register Default Bit 7 [2] General register set RHR XX bit THR XX bit IER 00 CTS interrupt 0 1 ...
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Table 7. SC16C852SV internal registers …continued [ Register Default Bit 7 [6] Enhanced register set EFR 00 Auto CTS Xon-1 00 bit Xon-2 00 bit 15 1 ...
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... NXP Semiconductors 7.1 Transmit (THR) and Receive (RHR) Holding Registers The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and Transmit Shift Register (TSR). The status of the THR is provided in the Line Status Register (LSR). Writing to the THR transfers the contents of the data bus (AD7 to AD0) to the transmit FIFO. The THR empty fl ...
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... NXP Semiconductors Table 8. Bit Symbol Description 1 IER[1] 0 IER[0] 7.2.1 IER versus Transmit/Receive FIFO interrupt mode operation When the receive FIFO is enabled (FCR[0] = logic 1), and receive interrupts (IER[0] = logic 1) are enabled, the receive interrupts and register status will reflect the following: • ...
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... NXP Semiconductors 7.3 FIFO Control Register (FCR) This register is used to enable the FIFOs, clear the FIFOs and set the receive FIFO trigger levels. 7.3.1 FIFO mode Table 9. Bit 7:6 5 [1] For 128-byte FIFO mode, refer to [2] For 128-byte FIFO mode, refer to ...
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... NXP Semiconductors Table 10. FCR[ [1] When RXINTLVL or TXINTLVL or FLWCNTH or FLWCNTL contains any value other than 0x00, receive and transmit trigger levels are set by RXINTLVL, TXINTLVL; see Table 11. FCR[ [1] When RXINTLVL or TXINTLVL or FLWCNTH or FLWCNTL contains any value other than 0x00, receive and transmit trigger levels are set by RXINTLVL, TXINTLVL; see ...
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... NXP Semiconductors 7.4 Interrupt Status Register (ISR) The SC16C852SV provides six levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the ISR will provide the user with the highest pending interrupt level to be serviced ...
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... NXP Semiconductors 7.5 Line Control Register (LCR) The Line Control Register is used to specify the asynchronous data communication format. The word length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. Table 14. Bit 7 6 5:3 2 1:0 Table 15 ...
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... NXP Semiconductors 7.6 Modem Control Register (MCR) This register controls the interface with the modem or a peripheral device. Table 18. Bit Symbol Description 7 MCR[7] Clock select 6 MCR[6] IR enable (see 5 MCR[5] Reserved; set to ‘0’. 4 MCR[4] Loopback. Enable the local Loopback mode (diagnostics). In this mode the ...
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... NXP Semiconductors 7.7 Line Status Register (LSR) This register provides the status of data transfers between the SC16C852SV and the CPU. Table 20. Bit Symbol 7 LSR[7] 6 LSR[6] 5 LSR[5] 4 LSR[4] 3 LSR[3] 2 LSR[2] 1 LSR[1] 0 LSR[0] SC16C852SV_1 Product data sheet Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface ...
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... NXP Semiconductors 7.8 Modem Status Register (MSR) This register shares the same address as EFCR register. This is a read-only register and it provides the current state of the control interface signals from the modem, or other peripheral device to which the SC16C852SV is connected. Four bits of this register are used to indicate the changed information ...
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... NXP Semiconductors 7.9 Extra Feature Control Register (EFCR) This is a write-only register, and it allows the software access to these registers: First Extra Register Set, Second Extra Register Set, Transmit FIFO Level Counter (TXLVLCNT), and Receive FIFO Level Counter (RXLVLCNT). Table 22. Bit 7:3 ...
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... NXP Semiconductors 7.14 Enhanced Feature Register (EFR) Enhanced features are enabled or disabled using this register. Bit 0 through bit 4 provide single or dual character software flow control selection. When the Xon1 and Xon2 and/or Xoff1 and Xoff2 modes are selected, the double 8-bit words are concatenated into two sequential numbers ...
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... NXP Semiconductors Table 24. Cont [1] When using a software flow control the Xon/Xoff characters cannot be used for data transfer. 7.15 Transmit Interrupt Level register (TXINTLVL) This 8-bit register is used store the transmit FIFO trigger levels used for interrupt generation. Trigger levels from 1 to 128 can be programmed with a granularity of 1. ...
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... NXP Semiconductors 7.17 Flow Control Trigger Level High (FLWCNTH) This 8-bit register is used to store the receive FIFO high threshold levels to start/stop transmission during hardware/software flow control. register bit settings; see Table 27. Bit 7:0 [1] For 32-byte FIFO mode, refer to 7.18 Flow Control Trigger Level Low (FLWCNTL) This 8-bit register is used to store the receive FIFO low threshold levels to start/stop transmission during hardware/software fl ...
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... NXP Semiconductors 7.20 Sampling Rate (SAMPR) Bit 1 and bit 0 of this register program the device’s sampling rate. Table 30. Bit 7:2 1:0 7.21 RS-485 turn-around time delay (RS485TIME) The value in this register controls the turn-around time of the external line transceiver in bit time. In automatic 9-bit mode, the RTSA/RTSB or DTRA/DTRB pin is used to control the direction of the line driver, after the last bit of data has been shifted out of the transmit shift register the UART will count down the value in this register ...
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... NXP Semiconductors Table 32. Bit 1 0 [1] It takes 4 XTAL1 clocks to reset the device. 7.23 Advanced Feature Control Register 2 (AFCR2) Table 33. Bit 7 SC16C852SV_1 Product data sheet Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface Advanced Feature Control Register 1 bits description ...
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... NXP Semiconductors 7.24 SC16C852SV external reset condition and software reset These two reset methods are identical and will reset the internal registers as indicated in Table 34. Table 34. Register IER FCR ISR LCR MCR LSR MSR EFCR SPR DLL DLM TXLVLCNT RXLVLCNT EFR XON1 ...
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... NXP Semiconductors 8. Limiting values Table 36. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol amb T stg P /pack total power dissipation per tot [1] V should not exceed 2 Static characteristics Table 37 + amb Symbol V IL(clk) V IH(clk LIL I LIH I L(clk DD(sleep) I DD(lp [1] Except XTAL2, V [2] Sleep current might be higher if there is any activity on the UART data bus during Sleep mode ...
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... NXP Semiconductors 10. Dynamic characteristics Table 38. Dynamic characteristics + 1. 1.95 V; unless otherwise specified. amb DD Symbol Parameter f frequency on pin XTAL1 XTAL1 t delay time from CS to LLA d(CS-LLA) t set-up time from address to LLA LOW su(A-LLAL) t LLA pulse width time w(LLA) t address hold time after LLA HIGH ...
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... NXP Semiconductors 10.1 Timing diagrams AD7 to AD0 CS LLA IOW Fig 8. General write timing AD7 to AD0 CS LLA IOR Fig 9. General read timing SC16C852SV_1 Product data sheet Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface upper address lower address t su(A-LLAH) ...
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... NXP Semiconductors IOW RTSA, RTSB change of state DTRA, DTRB CDA, CDB CTSA, CTSB DSRA, DSRB INTA, INTB IOR RIA, RIB Fig 10. Modem input/output timing external clock -------------- - XTAL1 t w clk Fig 11. External clock timing SC16C852SV_1 Product data sheet Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface ...
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... NXP Semiconductors RXA, RXB INTA, INTB IOR Fig 12. Receive timing TXA, TXB INTA, INTB active IOW Fig 13. Transmit timing SC16C852SV_1 Product data sheet Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface start bit data bits ( data bits 6 data bits ...
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... NXP Semiconductors TX data IrDA TX data Fig 14. Infrared transmit timing IrDA RX data RX data Fig 15. Infrared receive timing SC16C852SV_1 Product data sheet Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface UART frame start bit time bit time start Rev. 01 — 23 September 2008 ...
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... NXP Semiconductors 11. Package outline TFBGA36: plastic thin fine-pitch ball grid array package; 36 balls; body 3.5 x 3.5 x 0.8 mm ball A1 index area 1 ball A1 1 index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.25 0.90 0.35 mm 1.15 0.15 0.75 0.25 OUTLINE VERSION IEC ...
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... NXP Semiconductors 12. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 12.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 12.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 17. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 13. Abbreviations Table 41. Acronym CPU DLL DLM FIFO IrDA ISDN LSB MSB PCB RoHS UART VLIO 14 ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . . 7 6.1 UART A-B functions . . . . . . . . . . . . . . . . . . . . . 7 6.2 Extended mode (128-byte FIFO 6.3 Internal registers 6.4 FIFO operation . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.4.1 32-byte FIFO mode ...