H5TQ2G63BFR-H9C HYNIX SEMICONDUCTOR, H5TQ2G63BFR-H9C Datasheet - Page 19

• Manufacturer Part Number: H5TQ2G63BFR-H9C
• Description: 58T1898
• Manufacturer: HYNIX SEMICONDUCTOR

Specifications of H5TQ2G63BFR-H9C

• Memory Type: SDRAM
• Memory Configuration: 128M X 16
• Access Time: 13.5ns
• Interface Type: CMOS
• Memory Case Style: FBGA
• No. Of Pins: 96
• Operating Temperature Range: 0°C To +85°C
• Memory Size: 2 Gbit
• Rohs Compliant: Yes

Rev. 0.5 / Aug. 2010
1.8 Mode Register MR2
The Mode Register MR2 stores the data for controlling refresh related features, Rtt_WR impedance, and
CAS wire latency.The Mode Register 2 is written by asserting low on CS, RAS, CAS, We, high on BA1 and
low on BA0 and BA2, while controlling the states of address pins according to the table below.
MR2 Programming:
*1 : BA2, A5, A8, A11~A15 are RFU and must be programmed to 0 during MRS.
*2 : The Rtt_WR value can be applied during wirtes even when Rtt_Nom is disabled. During write leveling, Dynamic ODT is not available.
BA1
BA
0*
0
0
1
1
A10
1
2
0
0
1
1
BA
0
1
A7
1
1
0
1
A6
BA0
BA
Normal operating temperature
Extended (optional) operating
0
1
0
1
A9
0
0
1
0
1
0
Self-Refresh Temperature
Manual SR Reference (SRT)
A
15 ~
Auto-Self-Refresh (ASR)
temperature range
ASR enable (Optional)
Dynamic ODT off(Write does
MR mode
A
(SRT) Range
13
not affect Rtt value)
range
A
0*
12
MR0
MR1
MR2
MR3
1
Reserved
Rtt_WR*
RZQ/4
RZQ/2
A
11
A
Rtt_WR
10
2
A
9
Figure 8. MR2 Definition
A
0*
8
1
0
0
0
0
1
SRT
A5
A
7
0
0
0
0
1
1
1
1
A2
0
0
1
1
0
A4
ASR
A
6
0
0
1
1
0
0
1
1
A1
0
1
0
1
0
A3
A
5
0
1
0
1
0
1
0
1
A0
7 (1.875ns ≥ tCK(avg) ≥ 1.5ns)
8 (1.5ns ≥ tCK(avg) ≥ 1.25ns)
9 (1.25ns ≥ tCK(avg) ≥ 1.0ns)
CAS wirte Latency (CWL)
6 (2.5ns>tCK(avg ≥ 1.875ns)
CWL
A
4
3/4 Array (BA[2:0]=010,011,100,101,110&111)
Partial Array Self Refresh (Optional)
5 (tCK(avg) ≥ 2.5ns)
Half Array (BA[2:0]=000,001,010&011)
Half Array (BA[2:0]=100,101,110&111)
A
Quarter Array (BA[2:0]=000&001)
Quarter Array (BA[2:0]=110&111)
3
1/8th Array (BA[2:0]=000)
1/8th Array (BA[2:0]=111)
A
2
PASR
Full Array
A
1
H5TQ2G63BFR
A
0
Address Field
Mode Register 2
19