H5TQ2G63BFR-H9C HYNIX SEMICONDUCTOR, H5TQ2G63BFR-H9C Datasheet - Page 17

• Manufacturer Part Number: H5TQ2G63BFR-H9C
• Description: 58T1898
• Manufacturer: HYNIX SEMICONDUCTOR

Specifications of H5TQ2G63BFR-H9C

• Memory Type: SDRAM
• Memory Configuration: 128M X 16
• Access Time: 13.5ns
• Interface Type: CMOS
• Memory Case Style: FBGA
• No. Of Pins: 96
• Operating Temperature Range: 0°C To +85°C
• Memory Size: 2 Gbit
• Rohs Compliant: Yes

Rev. 0.5 / Aug. 2010
1.7.1 DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning
to normal operation after having the DLL disabled. During normal operation (DLL-on) with MR1 (A0 = 0), the DLL is auto-
matically disabled when entering Self-Refresh operation and is automatically re-enabled upon exit of Self-Refresh opera-
tion. Any time the DLL is enabled and subsequently reset, tDLLK clock cycles must occur before a Read or synchronous
ODT command can be issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait
for synchronization to occur may result in a violation of the tDQSCK, tAON or tAOF parameters. During tDLLK, CKE must
continuously be registered high. DDR3 SDRAM does not require DLL for any Write operation, except when RTT_WR is
enabled and the DLL is required for proper ODT operation. For more detailed information on DLL Disable operation refer
to “DLL-off Mode” on page 37.
The direct ODT feature is not supported during DLL-off mode. The on-die termination resistors must be disabled by con-
tinuously registering the ODT pin low and/or by programming the RTT_Nom bits MR1{A9,A6,A2} to {0,0,0} via a mode
register set command during DLL-off mode. The dynamic ODT feature is not supported at DLL-off mode. User must use
MRS command to set Rtt_WR, MR2 {A10, A9} = {0,0}, to disable Dynamic ODT externally.
1.7.2 Output Driver Impedance Control
The output driver impedance of the DDR3 SDRAM device is selected by MR1 (bits A1 and A5) as shown in Figure 7.
1.7.3 ODT Rtt Values
DDR3 SDRAM is capable of providing two different termination values (Rtt_Nom and Rtt_WR). The nominal termination
value Rtt_Nom is programmed in MR1. A seperate value (Rtt_WR) may be programmed in MR2 to enable a unique RTT
value when ODT is enabled during writes. The Rtt_WR value can be applied during writes even when Rtt_Nom is dis-
abled.
1.7.4 Additive Latency (AL)
Additive Latency (AL) operation is supported to make command and data bus dfficient for sustainable bandwidths in
DDR3 SDRAM. In this operation, the DDR3 SDRAM allows a read or write command (either with or without auto-pre-
charge) to be issued immediately after the active command. The command is held for the time of the Additive Latency
(AL) before it is issued inside the device. The Read Latency (RL) is controlled by the sum of the AL and CAS Latency (CL)
register settings. Write Latency (WL) is controlled by the sum of the AL and CAS Write Latency (CWL) register settings. A
summary of the AL register options are shown in Table.
1.7.5 Write leveling
For better signal integrity, DDR3 memory module adopted fly-by topology for the commands, addresses, control signals
and clocks. The fly-by topology has benefits from reducing number of stubs and their length but in other aspect, caused
flight time skew between clock and strobe at every DRAM on DIMM. It makes it difficult ofr the Controller to maintain
tDQSS, tDSS and tDSH specification. Therefore, the DDR3 SDRAM supports a ‘write leveling’ feature to allow the con-
troller to compensate for skew. See “Write Leveling” for mode details.
Note: AL has a value of CL - 1 or CL - 2 as per the CL values programmed in the MR0 register
0
0
1
1
A4
Table 3. Additive Latency (AL) Settings
1
1
0
1
A3
0 (AL Disabled)
Reserved
CL - 1
CL - 2
AL
H5TQ2G63BFR
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