MT48LC8M32B2B5-6 Micron Technology Inc, MT48LC8M32B2B5-6 Datasheet - Page 29

• Manufacturer Part Number: MT48LC8M32B2B5-6
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC8M32B2B5-6

• Organization: 8Mx32
• Density: 256Mb
• Address Bus: 14b
• Access Time (max): 17/7.5/5.5ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: FBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 165mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

Table 8:
Notes 1–11; notes appear below and on next page
NOTE:
09005aef8140ad6d
MT48LC8M32B2_2.fm - Rev. B 10/04 EN
CURRENT STATE
Any
Idle
Row Active
Read
(Auto Precharge
Disabled)
Write
(Auto Precharge
Disabled)
1. This table applies when CKE
2. This table is bank-specific, except where noted: i.e., the current state is for a specific bank and the commands shown are
3. Current state definitions:
4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP com-
state was self refresh).
those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below.
mands, or allowable commands to the other bank should be issued on any clock edge occurring during these states.
Allowable commands to the other bank are determined by its current state and Table 7, and according to Table 9.
Idle:
Row Active:
Read:
Write:
Precharging:
Row activating: Starts with registration of an ACTIVE command and ends when
Read with auto
precharge
enabled:
Write with auto
precharge
enabled:
Truth Table 3 – Current State Bank n, Command To Bank n
CS#
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
The bank has been precharged, and
A row in the bank has been activated, and
accesses and no register accesses are in progress.
A READ burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
A WRITE burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
Starts with registration of a PRECHARGE command and ends when
Once
t
Starts with registration of a READ command with auto precharge enabled and ends
when
Starts with registration of a WRITE command with auto precharge enabled and
ends when
n-1
RAS# CAS# WE#
RCD is met, the bank will be in the row active state.
H
H
H
H
H
H
H
H
H
X
L
L
L
L
L
L
L
was HIGH and CKE
t
t
RP is met, the bank will be in the idle state.
RP has been met. Once
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
t
RP has been met. Once
H
H
H
H
H
H
X
L
L
L
L
L
L
L
L
L
L
n
COMMAND INHIBIT (NOP/Continue previous operation)
NO OPERATION (NOP/Continue previous operation)
ACTIVE (Select and activate row)
AUTO REFRESH
LOAD MODE REGISTER
PRECHARGE
READ (Select column and start READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE (Deactivate row in bank or banks)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE (Truncate READ burst, start PRECHARGE)
BURST TERMINATE
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE (Truncate WRITE burst, start PRECHARGE)
BURST TERMINATE
is HIGH (see Table 7) and after
29
t
RP is met, the bank will be in the idle state.
t
RP is met, the bank will be in the idle state.
t
RP has been met.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
COMMAND (ACTION)
t
RCD has been met. No data bursts/
t
XSR has been met (if the previous
t
©2003 Micron Technology, Inc. All rights reserved.
RCD is met. Once
t
RP is met.
256Mb: x32
SDRAM
NOTES
11
10
10
10
10
10
10
7
7
8
8
9
8
9