MT48LC8M32B2B5-6 Micron Technology Inc, MT48LC8M32B2B5-6 Datasheet - Page 18

MT48LC8M32B2B5-6

Manufacturer Part Number
MT48LC8M32B2B5-6
Description
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet

Specifications of MT48LC8M32B2B5-6

Organization
8Mx32
Density
256Mb
Address Bus
14b
Access Time (max)
17/7.5/5.5ns
Maximum Clock Rate
166MHz
Operating Supply Voltage (typ)
3.3V
Package Type
FBGA
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
165mA
Pin Count
90
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT48LC8M32B2B5-6 TR
Manufacturer:
Micron Technology Inc
Quantity:
10 000
NOTE:
Data from any READ burst may be truncated with a
subsequent WRITE command, and data from a fixed-
length READ burst may be immediately followed by
data from a WRITE command (subject to bus turn-
around limitations). The WRITE burst may be initiated
on the clock edge immediately following the last (or
last desired) data element from the READ burst, pro-
09005aef8140ad6d
MT48LC8M32B2_2.fm - Rev. B 10/04 EN
Each READ command may be to either bank. DQM is LOW.
COMMAND
COMMAND
COMMAND
ADDRESS
ADDRESS
ADDRESS
CLK
CLK
CLK
DQ
DQ
DQ
Figure 11: Random READ Accesses
CL = 1
T0
T0
BANK,
BANK,
T0
BANK,
COL n
COL n
COL n
READ
READ
READ
CL = 2
CL = 3
T1
T1
T1
BANK,
BANK,
BANK,
READ
COL a
READ
COL a
READ
COL a
D
OUT
n
T2
T2
BANK,
BANK,
T2
COL x
COL x
READ
READ
READ
BANK,
COL x
D
D
OUT
OUT
n
a
18
T3
T3
T3
BANK,
COL m
BANK,
COL m
READ
READ
READ
BANK,
COL m
vided that I/O contention can be avoided. In a given
system design, there may be a possibility that the
device driving the input data will go Low-Z before the
SDRAM DQs go High-Z. In this case, at least a single-
cycle delay should occur between the last read data
and the WRITE command.
D
D
D
OUT
x
OUT
OUT
a
n
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T4
T4
T4
NOP
NOP
NOP
D
D
D
OUT
OUT
OUT
m
x
a
T5
T5
NOP
NOP
D
D
OUT
m
OUT
x
DON’T CARE
T6
NOP
D
OUT
m
©2003 Micron Technology, Inc. All rights reserved.
256Mb: x32
SDRAM

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