MT48LC8M32B2B5-6 Micron Technology Inc, MT48LC8M32B2B5-6 Datasheet - Page 28

• Manufacturer Part Number: MT48LC8M32B2B5-6
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC8M32B2B5-6

• Organization: 8Mx32
• Density: 256Mb
• Address Bus: 14b
• Access Time (max): 17/7.5/5.5ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: FBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 165mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

Table 7:
Notes 1–4
NOTE:
09005aef8140ad6d
MT48LC8M32B2_2.fm - Rev. B 10/04 EN
1. CKE
2. Current state is the state of the SDRAM immediately prior to clock edge n.
3. COMMAND
4. All states and sequences not shown are illegal or reserved.
5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n + 1 (provided
6. Exiting self refresh at clock edge n will put the device in the all banks idle state once
7. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at clock
CKE
that
NOP commands should be issued on any clock edges occurring during the
mands must be provided during
edge n + 1.
H
H
L
L
n-1
n
t
CKS is met).
is the logic state of CKE at clock edge n; CKE
CKE
H
H
L
L
n
n
Truth Table 2 – CKE
is the command registered at clock edge n, and ACTION
Reading or Writing
CURRENT STATE
Clock Suspend
Clock Suspend
All Banks Idle
All Banks Idle
Power-Down
Power-Down
Self Refresh
Self Refresh
t
XSR period.
COMMAND INHIBIT or NOP
COMMAND INHIBIT or NOP
COMMAND INHIBIT or NOP
See Truth Table 3
AUTO REFRESH
COMMAND
n-1
VALID
was the state of CKE at the previous clock edge.
X
X
X
X
28
n
Micron Technology, Inc., reserves the right to change products or specifications without notice.
n
is a result of COMMAND
t
XSR period. A minimum of two NOP com-
Maintain Clock Suspend
Maintain Power-Down
Maintain Self Refresh
Clock Suspend Entry
Power-Down Entry
Exit Clock Suspend
Self Refresh Entry
Exit Power-Down
Exit Self Refresh
ACTION
t
XSR is met. COMMAND INHIBIT or
n
©2003 Micron Technology, Inc. All rights reserved.
n
.
256Mb: x32
SDRAM
NOTES
5
6
7