MT48LC8M32B2B5-6 Micron Technology Inc, MT48LC8M32B2B5-6 Datasheet - Page 12

• Manufacturer Part Number: MT48LC8M32B2B5-6
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC8M32B2B5-6

• Organization: 8Mx32
• Density: 256Mb
• Address Bus: 14b
• Access Time (max): 17/7.5/5.5ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: FBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 165mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

CAS Latency
The CAS latency is the delay, in clock cycles, between
the registration of a READ command and the availabil-
ity of the first piece of output data. The latency can be
set to one, two, or three clocks.
If a READ command is registered at clock edge n, and
the latency is m clocks, the data will be available by
clock edge n + m. The DQs will start driving as a result
of the clock edge one cycle earlier (n + m - 1), and pro-
vided that the relevant access times are met, the data
will be valid by clock edge n + m. For example, assum-
ing that the clock cycle time is such that all relevant
access times are met, if a READ command is registered
at T0 and the latency is programmed to two clocks, the
DQs will start driving after T1 and the data will be valid
by T2, as shown in Figure 4. Table 5 indicates the oper-
ating frequencies at which each CAS latency setting
can be used.
Reserved states should not be used as unknown opera-
tion or incompatibility with future versions may result.
Operating Mode
The normal operating mode is selected by setting M7
and M8 to zero; the other combinations of values for
M7 and M8 are reserved for future use and/or test
modes. The programmed burst length applies to both
READ and WRITE bursts.
Test modes and reserved states should not be used
because unknown operation or incompatibility with
future versions may result.
Write Burst Mode
When M9 = 0, the burst length programmed via M0–
M2 applies to both READ and WRITE bursts; when M9
= 1, the programmed burst length applies to READ
bursts, but write accesses are single-location (non-
burst) accesses.
09005aef8140ad6d
MT48LC8M32B2_2.fm - Rev. B 10/04 EN
12
Table 5:
SPEED
COMMAND
COMMAND
COMMAND
-6
-7
CLK
CLK
CLK
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DQ
DQ
DQ
Figure 5: CAS Latency
READ
READ
READ
T0
T0
CL = 1
T0
CL = 1
t
t AC
≤50
≤50
LZ
CAS Latency
CL = 2
NOP
NOP
T1
NOP
T1
T1
t
t AC
LZ
CL = 3
D
t OH
OUT
ALLOWABLE OPERATING
CL = 2
©2003 Micron Technology, Inc. All rights reserved.
≤100
≤100
FREQUENCY (MHZ)
T2
T2
NOP
NOP
T2
t
t AC
LZ
256Mb: x32
D
t OH
OUT
SDRAM
T3
T3
NOP
D
t OH
CL = 3
OUT
≤166
≤143
DON’T CARE
UNDEFINED
T4