MT48LC8M32B2B5-6 Micron Technology Inc, MT48LC8M32B2B5-6 Datasheet - Page 22

• Manufacturer Part Number: MT48LC8M32B2B5-6
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC8M32B2B5-6

• Organization: 8Mx32
• Density: 256Mb
• Address Bus: 14b
• Access Time (max): 17/7.5/5.5ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: FBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 165mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

for a fixed-length WRITE burst may be immediately
followed by data for a WRITE command. The new
WRITE command can be issued on any clock following
the previous WRITE command, and the data provided
coincident with the new command applies to the new
command. An example is shown in Figure 18. Data n +
1 is either the last of a burst of two or the last desired of
a longer burst. This 256Mb SDRAM uses a pipelined
NOTE:
09005aef8140ad6d
MT48LC8M32B2_2.fm - Rev. B 10/04 EN
BL = 2. DQM is LOW.
COMMAND
ADDRESS
Figure 17: WRITE Burst
CLK
DQ
WRITE
BANK,
COL n
T0
D
n
IN
NOP
n + 1
T1
D
IN
NOP
T2
DON’T CARE
Figure 16: WRITE Command
T3
NOP
BA0, BA1
A9, A11
A0–A8
RAS#
CAS#
WE#
CKE
A10
CLK
CS#
HIGH
VALID ADDRESS
DISABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
22
ADDRESS
COLUMN
ADDRESS
architecture and therefore does not require the 2n rule
associated with a prefetch architecture. A WRITE com-
mand can be initiated on any clock cycle following a
previous WRITE command. Full-speed random write
accesses within a page can be performed to the same
bank, as shown in Figure 19 on page 23, or each subse-
quent WRITE may be performed to a different bank.
NOTE:
BANK
DQM is LOW. Each WRITE command may be to any
bank.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DON’T CARE
Figure 18: WRITE to WRITE
COMMAND
ADDRESS
CLK
DQ
WRITE
BANK,
COL n
D
T0
n
IN
©2003 Micron Technology, Inc. All rights reserved.
n + 1
NOP
T1
D
IN
256Mb: x32
DON’T CARE
WRITE
BANK,
COL b
T2
D
b
IN
SDRAM