MT48LC8M32B2B5-6 Micron Technology Inc, MT48LC8M32B2B5-6 Datasheet - Page 20

MT48LC8M32B2B5-6

Manufacturer Part Number
MT48LC8M32B2B5-6
Description
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet

Specifications of MT48LC8M32B2B5-6

Organization
8Mx32
Density
256Mb
Address Bus
14b
Access Time (max)
17/7.5/5.5ns
Maximum Clock Rate
166MHz
Operating Supply Voltage (typ)
3.3V
Package Type
FBGA
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
165mA
Pin Count
90
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT48LC8M32B2B5-6 TR
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Full-page READ bursts can be truncated with the
BURST TERMINATE command, and fixed-length
READ bursts may be truncated with a BURST TERMI-
NATE command, provided that auto precharge was
not activated. The BURST TERMINATE command
should be issued x cycles before the clock edge at
NOTE:
09005aef8140ad6d
MT48LC8M32B2_2.fm - Rev. B 10/04 EN
DQM is LOW.
COMMAND
COMMAND
COMMAND
ADDRESS
ADDRESS
ADDRESS
CLK
CLK
CLK
DQ
DQ
DQ
BANK a,
BANK a,
BANK a,
COL n
COL n
COL n
T0
T0
T0
Figure 14: READ-to-PRECHARGE
READ
READ
READ
CL = 1
CL = 2
T1
T1
T1
NOP
NOP
NOP
D
OUT
CL = 3
n
T2
T2
T2
NOP
NOP
NOP
D
n + 1
D
OUT
OUT
n
T3
T3
T3
20
NOP
NOP
NOP
D
n + 2
D
D
n + 1
OUT
OUT
OUT
n
which the last desired data element is valid, where x
equals the CAS latency minus one. This is shown in
Figure 15 on page 21 for each possible CAS latency;
data element n + 3 is the last desired data element of a
longer burst.
PRECHARGE
PRECHARGE
PRECHARGE
(a or all)
(a or all)
(a or all)
T4
BANK
T4
BANK
T4
BANK
X = 0 cycles
X = 1 cycle
D
n + 3
D
n + 2
D
n + 1
OUT
OUT
OUT
Micron Technology, Inc., reserves the right to change products or specifications without notice.
X = 2 cycles
T5
T5
T5
NOP
NOP
NOP
D
n + 3
D
n + 2
OUT
OUT
t RP
t RP
t RP
T6
T6
T6
NOP
NOP
NOP
D
n + 3
OUT
DON’T CARE
BANK a,
BANK a,
BANK a,
ACTIVE
ACTIVE
ACTIVE
T7
T7
T7
ROW
ROW
ROW
©2003 Micron Technology, Inc. All rights reserved.
256Mb: x32
SDRAM

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