MT48LC8M32B2B5-6 Micron Technology Inc, MT48LC8M32B2B5-6 Datasheet - Page 13

• Manufacturer Part Number: MT48LC8M32B2B5-6
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC8M32B2B5-6

• Organization: 8Mx32
• Density: 256Mb
• Address Bus: 14b
• Access Time (max): 17/7.5/5.5ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: FBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 165mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

Commands
Table 6 provides a quick reference of available com-
mands. This is followed by a written description of
each command. Three additional Truth Tables (Tables
Table 6:
Note 1
NOTE:
COMMAND INHIBIT
The COMMAND INHIBIT function prevents new com-
mands from being executed by the SDRAM, regardless
of whether the CLK signal is enabled. The SDRAM is
effectively deselected. Operations already in progress
are not affected.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to per-
form a NOP to an SDRAM which is selected (CS# is
LOW). This prevents unwanted commands from being
registered during idle or wait states. Operations
already in progress are not affected.
09005aef8140ad6d
MT48LC8M32B2_2.fm - Rev. B 10/04 EN
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
LOAD MODE REGISTER
Write Enable/Output Enable
Write Inhibit/Output High-Z
1. CKE is HIGH for all commands shown except SELF REFRESH.
2. A0–A11 define the op-code written to the mode register.
3. A0–A11 provide row address, BA0 and BA1 determine which bank is made active.
4. A0–A8 provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables
5. A10 LOW: BA0 and BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0 and BA1 are
6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay). DQM0 controls DQ0–
the auto precharge feature; BA0 and BA1 determine which bank is being read from or written to.
“Don’t Care.”
DQ7; DQM1 controls DQ8–DQ15; DQM2 controls DQ16–DQ23; and DQM3 controls DQ24–DQ31.
Truth Table 1 – Commands and DQM Operation
NAME (FUNCTION)
CS#
H
L
L
L
L
L
L
L
L
–
–
13
7, 8, and 9) appear following “Operations” on page 15;
these tables provide current state/next state informa-
tion.
LOAD MODE REGISTER
The mode register is loaded via inputs A0–A11. See
mode register in “Register Definition” on page 10. The
LOAD MODE REGISTER command can only be issued
when all banks are idle, and a subsequent executable
command cannot be issued until
ACTIVE
The ACTIVE command is used to open (or activate) a
row in a particular bank for a subsequent access. The
value on the BA0 and BA1 inputs selects the bank, and
the address provided on inputs A0–A11 selects the row.
This row remains active (or open) for accesses until a
PRECHARGE command is issued to that bank. A PRE-
CHARGE command must be issued before opening a
different row in the same bank.
RAS#
H
X
H
H
H
L
L
L
L
–
–
Micron Technology, Inc., reserves the right to change products or specifications without notice.
CAS# WE# DQM
X
H
H
H
H
L
L
L
L
–
–
H
H
H
H
X
L
L
L
L
–
–
L/H
L/H
X
X
X
X
X
X
X
H
L
8
8
Bank/Row
©2003 Micron Technology, Inc. All rights reserved.
Bank/Col
Bank/Col
Op-Code
ADDR
Code
X
X
X
X
–
–
256Mb: x32
t
MRD is met.
High-Z
Active
Active
Valid
SDRAM
DQS
X
X
X
X
X
X
X
NOTES
6, 7
3
4
5
2
8
4
8