PDI1394L40BE,551 NXP Semiconductors, PDI1394L40BE,551 Datasheet - Page 9

• Manufacturer Part Number: PDI1394L40BE,551
• Manufacturer: NXP Semiconductors

Specifications of PDI1394L40BE,551

• Lead Free Status / Rohs Status: Compliant

Philips Semiconductors
9.2 AV Interface 1
NOTE: This AV interface may be configured to transmit or receive according to the condition of “DIRAV1” bit in GLOBCSR register
(0x018)—default is transmit.
2000 Dec 15
117, 116, 115, 114,
111, 110, 109, 108
1394 enhanced AV link layer controller
PIN No.
100
101
102
103
118
96
97
98
99
PIN SYMBOL
AV1ENDPCK
AV1FSYNC
AV1READY
AV1 D[7:0]
AV1VALID
AV1SYNC
AV1ERR0
AV1ERR1
AV1CLK
AV1 SY
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
I
I
CRC error. Indicates bus packet delivered on AV1 D[7:0] had a CRC error; the current AV
packet is unreliable.
Sequence Error. Indicates at least one source packet was lost before the current AV1 D [7:0] data.
End of application packet indication from data source. Required only if input packet is not
multiple of 4 bytes. It can be tied LOW for data packets that are 4*N in size.
External application clock. Rising edge active. This pin can be programmed to be an output
and the application clock. Depending on the configuration of AV Port 1 as transmitter or receiver,
the output enable is located in the ITXPKCTL register (address 0x020) or IRXPKCTL register
(address 0x040).
Programmable frame sync, is set to input when AV interface 1 is a transmitter and to output
when the interface is configured as a receiver. When the pin is an input, it is used to designate
a frame of data for Digital Video (DV). The signal is time stamped and transmitted in the SYT
field of ITXHQ2. When set to an output, the signal is derived from SYT field of IRXHQ2.
SY Value. When port AV1 is configured as a transmitter, this pin is an input. When the AV port
is configured to as a receiver, the pin is an output. See the description for bit 0 of the
ITXCTL (0x034) and IRXCTL (0x054) registers.
Indicates data on AV1 D [7:0] is valid.
Indicates that the data currently being clocked by the source under the condition of AV1VALID
is the start of an application packet. If the AV interface is configured as a receiver, then it will
assert AV1SYNC when an application packet becomes available and persist until the first data
of the packet is clocked out. Thus, AV1VALID may last for more than one cycle, but for exactly
one cycle in which AV1VALID is asserted.
Audio/Video Data 7 (MSB) through 1. Part of byte-wide interface to the AV layer 1.
When the AV port is configured as a receiver, this pin is an input. This is a flow control signal
that allows the application to indicate whether it is able to accept data flowing across
AV Interface 1. The AV interface responds to an inactive AV1READY by not asserting
AV1VALID, and thereby withholding data from the application.
The AV1READY signal is processed through one level of pipelining, which means that the
AV Link will accept data on the cycle in which AV1READY is de-asserted and will not accept
data on the cycle in which AV1READY is asserted.
When the AV port is configured to transmit, this pin is an output. This is a flow control signal
that allows the link chip to indicate whether it is able to accept data flowing across AV Interface
1. The source of data, an external entity, responds to an inactive AV1READY by not asserting
AV1VALID, and thereby withholding data.
The AV1READY signal should be processed by the sink through one level of pipelining, which
means that the receiver must be able to accept data on the cycle in which AV1READY is
de-asserted. The receiving interface does not have to accept data on the cycle in which
AV1READY is asserted.
5
NAME AND FUNCTION
PDI1394L40
Preliminary specification