PDI1394L40BE,551 NXP Semiconductors, PDI1394L40BE,551 Datasheet - Page 81

• Manufacturer Part Number: PDI1394L40BE,551
• Manufacturer: NXP Semiconductors

Specifications of PDI1394L40BE,551

• Lead Free Status / Rohs Status: Compliant

E–4
When L40 is used with IEEE 1394–1995 compatible PHYs, RDI register bit ”PLI” does not function.
Description of expected operation: When the L40 is placed in power–down mode (either by setting the SWPD bit in the RDI register
or placing the PD pin in the HIGH state), the L40 stops producing the LPS signal and the PHY interprets this lack of LPS signal as a
request to remove the SYSCLK (system clock) from the link – PHY interface. This action causes the L40 to enter power–down mode
and should place the SCA bit LOW, the PLI bit LOW, and the SCI bit HIGH.
Description of observed behavior: The PLI bit (bit 3) always indicates a set (1) condition regardless of whether the L40 is powered up
or powered down. This is normal bit PLI operation when the L40 is used with a NON 1394A type of PHY.
Solution or work around: Non–1394A PHYs do not initialize the link–PHY interface... this is normal functioning. When the L40 is
operated with its 1394 MODE pin held high (as is the case when operating with a 1394–1995 PHY) the PLI bit in the RDI register will
always be seen as set (1). In order to determine the status of operation of the L40, the SCA and SCI bits may be used (SCI bit recom-
mended) to determine the power status of the link chip. The PLI bit should be ignored by the node operating software when the L40 is
operated with a NON–1394A PHY with the L40 1394 MODE pin at 3.3v (high).
Philips Semiconductors
Errata To the PDI1394L40 1394 AV Link Layer Controller (Data Sheet dated: 2000 December 15).
15 December 2000 – Page 77