PDI1394L40BE,551 NXP Semiconductors, PDI1394L40BE,551 Datasheet - Page 65

• Manufacturer Part Number: PDI1394L40BE,551
• Manufacturer: NXP Semiconductors

Specifications of PDI1394L40BE,551

• Lead Free Status / Rohs Status: Compliant

Philips Semiconductors
13.3.7 Asynchronous Receive Request (RREQ) – Base Address: 0x098
Reset Value 0x00000000
Bit 31..0:
13.3.8 Asynchronous Receive Response (RRSP) – Base Address: 0x09C
Reset Value 0x00000000
Bit 31..0:
13.3.9 Asynchronous RX/TX Interrupt Acknowledge (ASYINTACK) – Base Address: 0x0A0
Reset Value 0x00000C00
Bit 31..17:
Bit 16:
Bit 15:
Bit 14:
Bit 13:
Bit 12:
Bit 11:
Bit 10:
Bit 9:
Bit 8:
Bit 7:
Bit 6:
Bit 5:
Bit 4:
Bit 3:
Bit 2:
Bit 1:
Bit 0:
2000 Dec 15
1394 enhanced AV link layer controller
R
Reading this register will clear the RREQQQAV flag until the next received quadlet is available for reading.
R
Reading this register will clear the RRSPQQAV flag until the next received quadlet is available for reading.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
31 30
29 28 27 26 25 24 23
RREQ:Quadlet of packet from receiver request queue (transfer register).
RRSP:Quadlet of packet from receiver response queue (transfer register).
Unused bits read ‘0’
RRSPQFULL: Receiver response queue did become full. Write a “1” to this bit to reset the interrupt.
RREQQFULL: Receiver request queue did become full. Write a “1” to this bit to reset the interrupt.
SIDQAV: Current quadlet in RREQ is selfID data. This bit is set only after a bus reset, not after reception of PHY
packets other than self IDs. This interrupt automatically resets when the quadlet is read.
RRSPQLASTQ: Current quadlet in RRSP is last quadlet of packet. This interrupt automatically resets when the
quadlet is read.
RREQQLASTQ: Current quadlet in RREQ is last quadlet of packet. This interrupt automatically resets when the
quadlet is read.
RRSPQRDERR: Receiver response queue read error (transfer error) or bus reset occurred.
When set (1), this queue is blocked for read access. Write a “1” to this bit to reset the interrupt.
RREQQRDERR: Receiver request queue read error (transfer error) or bus reset occurred.
When set (1), this queue is blocked for read access. Write a “1” to this bit to reset the interrupt.
RRSPQQAV: Receiver response queue quadlet available (in RRSP). This interrupt automatically resets when the
quadlet is read.
RREQQQAV: Receiver request queue quadlet available (in RREQ). This interrupt automatically resets when the
quadlet is read.
TIMEOUT: Split transaction response timeout. Write a “1” to this bit to reset the interrupt.
RCVDRSP: Solicited response received (within timeout interval). Write a “1” to this bit to reset the interrupt.
TRSPQFULL: Transmitter response queue did become full. Write a “1” to this bit to reset the interrupt.
TREQQFULL: Transmitter request queue did become full. Write a “1” to this bit to reset the interrupt.
TRSPQWRERR: Transmitter response queue write error (transfer error). Write a “1” to this bit to reset the interrupt.
TREQQWRERR: Transmitter request queue write error (transfer error). Write a “1” to this bit to reset the interrupt.
TRSPQWR: Transmitter response queue written (transfer register emptied). Write a “1” to this bit to reset the interrupt.
TREQQWR: Transmitter request queue written (transfer register emptied). Write a “1” to this bit to reset the interrupt.
3130
31 30
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
22 21 20 19 18 17 16 15 14 13 12 11 10
RREQ
RRSP
61
9
8
SV00298
SV00297
7
6
5
4
3
2
SV00796
PDI1394L40
1
Preliminary specification
0