PDI1394L40BE,551 NXP Semiconductors, PDI1394L40BE,551 Datasheet - Page 19

• Manufacturer Part Number: PDI1394L40BE,551
• Manufacturer: NXP Semiconductors

Specifications of PDI1394L40BE,551

• Lead Free Status / Rohs Status: Compliant

are continuous; so we recommend that before the interrupt is acknowledged, the corresponding enable bit should be set to “0”, else the interrupt
Philips Semiconductors
will immediately happen again.]
SWPD is a control bit. There are two ways to affect a power–down of the link chip. Setting SWPD will stop the link chip from transmitting the
LPS signal to the phy chip and thus cause the phy to withhold the SCLK, thus powering–down the link chip. Raising the link PD pin to the high
level will also accomplish power–down in a similar manner. DO NOT USE BOTH METHODS to affect a power–down. The SWPD bit, being a
control bit, will NOT reflect the state of the PD pin. If the SWPD bit is = 0 and the SCI bit is = 1, it’s a good bet that the PD pin is active if the phy
chip is operating. In this case the PD pin MUST be reset low before the link will power–up.
EPLI, ELOA, ESCA, and ESCI are interrupt enable bits. Setting any of these bits = 1 will cause the corresponding interrupt bit to become an
active interrupt when that bit sets. If these bits are set = 0, the corresponding PLI, LOA, SCA, and SCI bit is in the interrupt/status mode as
described above.
(Also see the individual bit descriptions in the RDI register section of this data sheet... Section 13.3.1)
12.5.4 Big and little endianness, data invariance, and data bus width
The host interface offers programmable endianness, data invariance, and selectable 8 and 16 bit data widths. LTLEND (pin 121) and DATINV
(pin 122) are multiplexed configuration pins that will be sampled on the trailing edge of RESET; the states of these pins are established by
connecting each pin to the proper logic state, ground or V
register (0x0F4) will be preset to a value of 0x0F0A0500 after a power reset. Table 1 describes the configurations.
Table 1. Configuration possible combinations
Table 2. Explanation of the mode LittleEnd = 1, DataInvariant = 1
It is important to note that some operands in the indirect address space consist of more than one quadlet. For these operands, the lowest
address always contains the most significant quadlet.
In Bit Endian mode and DATAINV = 0, the bytes in each quadlet are numbered 0..3 from left (most significant) to right (least significant) as
shwon in Figure 4.
To access a register in 8 bit HIF mode, at address N the CPU should use addresses E:
E = N ; to access the upper 8 bits of the register.
E = N + 1 ; to access the upper middle 8 bits of the register.
E = N + 2 ; to access the lower middle 8 bits of the register.
E = N + 3 ; to access the lower 8 bits of the register.
To access a register in 16 bit HIF mode, at internal address N, the CPU should use addresses E:
E = N ;to access the upper 16 bits of the register
E = N + 2 ;to access the lower 16 bits of the register
2000 Dec 15
1394 enhanced AV link layer controller
Outside Address (A1, A0)
LTLEND (Little Endian)
00
01
10
11
1
1
0
0
Figure 4. Byte order in quadlets as implemented in the host interface, HIF LTLEND = LOW
HIF16 = 0
3130
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BYTE 0
DATINV (Data Invariant)
Inside Address (A1, A0)
11
10
01
00
1
0
X
X
DD
BYTE 1
, through a resistor, 22 k is recommended. To verify the configuration, the shadow
15
Outside Address (A1, A0)
See Table 2
BYTE 2
HIF 16BIT
1
1
0
0X
0X
1X
1X
BYTE 3
Byte/Word address is reversed
Bytes are swapped within the word
16-bit data bus, address as in PDI1394L21
8-bit data bus, address as in PDI1394L21
SV00656
HIF16 = 1
Inside Address (A1, A0)
Result
PDI1394L40
Preliminary specification
1X
1X
0X
0X