PDI1394L40BE,551 NXP Semiconductors, PDI1394L40BE,551 Datasheet - Page 21

• Manufacturer Part Number: PDI1394L40BE,551
• Manufacturer: NXP Semiconductors

Specifications of PDI1394L40BE,551

• Lead Free Status / Rohs Status: Compliant

In non-multiplex mode (HIF MUX = LOW), an access through the host interface starts when HIF CSN = 0 and either HIF WRN = 0 or HIF RDN = 0.
In multiplex mode (HIF MUX = HIGH), an access through the host interface starts when HIF CSN = 0 and either HIF WRN = 0 or HIF RD_N = 0.
1. ALE line is held LOW.
Philips Semiconductors
12.5.6 The CPU bus interface signals
The CPU interface is directly compatible with a wide range of microcontrollers, and supports both multiplexed and non-multiplex access. It uses
separate HIF RDN, HIF WRN, HIF ALE, and HIF CSN chip select lines. There are 9 address inputs (HIF A0..HIF A8) and 8 or 16 data in/out
lines HIF D[7:0] or HIF D [15:0]. The upper 8 bits of the data in/out lines are only used when the 8/16 bit mode pin (HIF16BIT) is held HIGH.
The CPU is not required to run a clock that is synchronous to the 1394 base clock. The control signals will be resampled by the host interface
before being used internally.
Typically the chip select signal is derived from the upper address lines of the CPU (address decode stage), but it could also be connected to a
port pin of the CPU to avoid the need for an external address decoder in very simple CPU systems. When both HIF CSN = 0 and HIF RDN = 0
the host interface will start a read access cycle, so the cycle is triggered at the falling edge of either HIF CSN or HIF RDN, whichever is later.
The address must now be presented on the HIF AD [7:0] lines, and will be latched on the falling edge of ALE. If HIF RDN = 0, data will be
offered after the falling edge of ALE. If HIF WRN = 0, data has to be presented by the microcontroller.
In both multiplexed and non-multiplexed mode, HIF WAIT can be used to signal to the controlling CPU that an extension of the current access
cycle is needed. This allows the PDI1394L40 to work in the same address space as peripherals with a shorter access time. HIF WAIT will
remain HIGH for the minimum duration of the access cycle. If HIF A[8] is HIGH, HIF WAIT will extend the access cycle to 120ns to allow for the
shadow register transfer to take place. Subsequent access to the same register which does not required A[8] to be raised, can be executed
much faster. By connecting HIF WAIT to the appropriate input on the controlling processor, the PDI1394L40 can be mapped in memory space
with faster devices. The PDI1394L40 should not be mapped in memory space with devices that require access faster than 15 ns.
HIF A[7:0] can be used as a simple demultiplexer. In multiplex mode, the address on AD[7:0] will appear on A[7:0] immediately, and will remain
there until the next rising edge of HIF ALE.
NOTE:
2000 Dec 15
1394 enhanced AV link layer controller
An extended read cycle may be implemented by holding CS_N and RD_N low (active) and changing only the A7–A0 address.
After each new address stabilizes, wait at least t
read of the first byte of the shadow register using the A8 transfer mechanism. See the section on Read Accesses (12.5.1).
HIFAD7–AD0
HIFD15–D8
HIF WR_N
HIF CS_N
HIF RD_N
HIFA7–A0
HIF_WAIT
HIF_MUX
HIF16BIT
HIF A8
Figure 6. 16 Bit Read Cycle Non-multiplexed
ACC
and read the data. The extended read cycle can be used only following a
17
PDI1394L40
Preliminary specification
SV01088