PDI1394L40BE,551 NXP Semiconductors, PDI1394L40BE,551 Datasheet - Page 52

• Manufacturer Part Number: PDI1394L40BE,551
• Manufacturer: NXP Semiconductors

Specifications of PDI1394L40BE,551

• Lead Free Status / Rohs Status: Compliant

Philips Semiconductors
13.1.4 Link / Phy Interrupt Enable (LNKPHYINTE) – Base Address: 0x00C
This register is a mirror of the Link/Phy Interrupt Acknowledge (LNKPHYINTACK) register. Enabling an interrupt is accomplished by writing a ‘1’
to the bit corresponding to the interrupt desired.
This register enables the interrupts described in the Link /Phy Interrupt Acknowledge register (LNKPHYINTACK) description. A one in any of the
bits enables that function to create an interrupt. A zero disables the interrupt, however the status is readable in the Link /Phy Interrupt
Acknowledge register.
Reset Value 0x00000000
13.1.5 Cycle Timer Register (CYCTM) – Base Address: 0x010
Cycle Timer Register operation is controlled by the Cycle Timer Enable (CYTMREN) bit in the Link Control Register (LNKCTL, 0x004). If the
Cycle Timer Register is disabled, it can be used as a general read write register for Host Interface Firmware testing.
Reset Value 0x00000000
Bit 31..25:
Bit 24..12:
Bit 11..0:
2000 Dec 15
1394 enhanced AV link layer controller
Bits 21..0 are interrupt enable bits for the Link/Phy Interrupt Acknowledge (LNKPHYINTACK).
R/W
R/W
R/W
Seconds count: 1-Hz cycle timer counter.
Cycle Number: 8kHz cycle timer counter.
Cycle Offset: 24.576MHz cycle timer counter.
31 30
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
3130
CYCLE_SECONDS
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CYCLE_NUMBER
48
CYCLE_OFFSET
SV00276
SV01841
PDI1394L40
Preliminary specification