PDI1394L40BE,551 NXP Semiconductors, PDI1394L40BE,551 Datasheet - Page 15

• Manufacturer Part Number: PDI1394L40BE,551
• Manufacturer: NXP Semiconductors

Specifications of PDI1394L40BE,551

• Lead Free Status / Rohs Status: Compliant

Philips Semiconductors
DEFAULT BUFFER SIZE
12.3 Bushold and Link/PHY single capacitor galvanic isolation
12.3.1 Bushold
The PDI1394L40 uses an internal bushold circuit on each of the indicated pins to keep these CMOS inputs from “floating” while being driven by
a 3-Stated device or input coupling capacitor. Unterminated high impedance inputs react to ambient electrical noise which cause internal
oscillation and excess power supply current draw.
The following pins have bushold circuitry enabled when the ISON pin is in the logic “1” state:
Philips bushold circuitry is designed to provide a high resistance pull-up or pull-down on the input pin. This high resistance is easily overcome
by the driving device when its state is switched. Figure 2 shows a typical bushold circuit applied to a CMOS input stage. Two weak MOS
transistors are connected to the input. An inverter is also connected to the input pin and supplies gate drive to both transistors. When the input
is LOW, the inverter output drives the lower MOS transistor and turns it on. This re-enforces the LOW on the input pin. If the logic device which
normally drives the input pin were to be 3-Stated, the input pin would remain “pulled-down” by the weak MOS transistor. If the driving logic
device drives the input pin HIGH, the inverter will turn the upper MOS transistor on, re-enforcing the HIGH on the input pin. If the driving logic
device is then 3-Stated, the upper MOS transistor will weakly hold the input pin HIGH.
The PHY’s outputs can be 3-Stated and single capacitor isolation can be used with the Link; both situations will allow the Link inputs to float.
With bushold circuitry enabled, these pins are provided with dc paths to ground, and power by means of the bushold transistors; this
arrangement keeps the inputs in known logical states.
2000 Dec 15
1394 enhanced AV link layer controller
Name
PHY CTL0
PHY CTL1
PHY D0
PHY D1
PHY D2
PHY D3
PHY D4
PHY D5
PHY D6
PHY D7
SYSCLK
Function
PHY control line 0
PHY control line 1
PHY data bus bit 0
PHY data bus bit 1
PHY data bus bit 2
PHY data bus bit 3
PHY data bus bit 4
PHY data bus bit 5
PHY data bus bit 6
PHY data bus bit 7
System clock input to the link
Asynchronous Transmit Response FIFO
Asynchronous Receive Response FIFO
Asynchronous Transmit Request FIFO
Asynchronous Receive Request FIFO
Isochronous (AV) Transmit Buffer
Isochronous (AV) Receive Buffer
BUFFER MEMORY
INPUT PIN
Figure 2. Bushold circuit
11
INTERNAL
CIRCUITS
SV00911
PDI1394L40
Preliminary specification
(Quadlets)
SIZE
1024
1024
256
256
256
256