EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 772

• Manufacturer Part Number: EP1S20F780I6N
• Description: IC STRATIX FPGA 20K LE 780-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F780I6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 586
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 18460
• # I/os (max): 586
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 18460
• Ram Bits: 1669248
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Device Configuration Pins
11–54
Stratix Device Handbook, Volume 2
CONF_DONE
nCE
Table 11–15. Dedicated Configuration Pins on the Stratix or Stratix GX Device
Pin Name
N/A
N/A
User Mode
All
All
Configuration
Scheme
Bidirectional
open-drain
Input
Pin Type
Status output. The target FPGA drives the
CONF_DONE
configuration. Once all configuration data is
received without error and the initialization
cycle starts, the target device releases
CONF_DONE
Status input. After all data is received and
CONF_DONE
initializes and enters user mode. The
CONF_DONE pin must have an external
10-k pull-up resistor in order for the device to
initialize.
Driving
and initialization does not affect the configured
device.
The enhanced configuration devices’ and
EPC2 devices’
internal programmable pull-up resistors. If
internal pull-up resistors on the enhanced
configuration device are used, external 10-k
pull-up resistors should not be used on these
pins. When using EPC2 devices, only external
10-k pull-up resistors should be used.
This pin uses Schmitt trigger input buffers.
Active-low chip enable. The
the device with a low signal to allow
configuration. The
during configuration, initialization, and user
mode. In single device configuration, it should
be tied low. In multi-device configuration,
of the first device is tied low while its
is connected to
chain.
The
successful JTAG programming of the FPGA.
This pin uses Schmitt trigger input buffers.
nCE
CONF_DONE
pin must also be held low for
.
pin low before and during
goes high, the target device
OE
nCE
Description
and
nCE
(Part 4 of 8)
of the next device in the
low after configuration
nCS
pin must be held low
Altera Corporation
pins have optional
nCE
pin activates
nCEO
July 2005
nCE
pin