EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 482
EP1S20F780I6N
Manufacturer Part Number
EP1S20F780I6N
Description
IC STRATIX FPGA 20K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S20F780I6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
586
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
18460
# I/os (max)
586
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
18460
Ram Bits
1669248
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F780I6N
Manufacturer:
ALTERA
Quantity:
3 000
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Principles of SERDES Operation
Figure 5–6. Transmitter Timing Diagram
5–10
Stratix Device Handbook, Volume 2
Internal ×10 clock
Internal ×1 clock
TXLOADEN
data input
Receiver
n – 1
Transmitter Clock Output
Different applications and protocols call for various clocking schemes.
Some applications require you to center-align the rising or falling clock
edge with the data. Other applications require a divide version of the
transmitted clock, or the clock and data to be at the same high-speed
frequency. The Stratix device transmitter clock output is versatile and
easily programmed for all such applications.
Stratix devices transmit data using the source-synchronous scheme,
where the clock is transmitted along with the serialized data to the
receiving device. Unlike APEX
devices do not have a fixed transmitter clock output pin. The Altera
Quartus II software generates the transmitter clock output by using a fast
clock to drive a transmitter dataout channel. Therefore, you can place
the transmitter clock pair close to the data channels, reducing clock-to-
data skew and increasing system margins. This approach is more flexible,
as any channel can drive a clock, not just specially designated clock pins.
Divided-Down Transmitter Clock Output
You can divide down the high-frequency clock by 2, 4, 8, or 10, depending
on the system requirements. The various options allow Stratix devices to
accommodate many different types of protocols. The divided-down clock
is generated by an additional transmitting data channel.
n – 0
9
8
7
6
TM
20KE and APEX II devices, Stratix
5
4
3
2
Altera Corporation
1
0
July 2005
®
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