EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 690

• Manufacturer Part Number: EP1S20F780I6N
• Description: IC STRATIX FPGA 20K LE 780-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F780I6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 586
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 18460
• # I/os (max): 586
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 18460
• Ram Bits: 1669248
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

General Architecture
10–6
Stratix Device Handbook, Volume 2
Note to
(1)
Blocks
Logic
Pins
Architectural
Table 10–3. Stratix & Stratix GX Location Assignment Syntax
Elements
You can make assignments to I/O pads using IOC_X<number>_Y<number>_N<number>.
(1)
Table
10–3:
LAB, DSP,
DSPOUT, M512,
M4K, M-RAM
LE, IOC, PLL,
DSPMULT,
SERDESTX,
SERDESRX
I/O pins
Element Name
Table 10–3
Stratix GX devices.
Use the following guidelines with the new naming system:
■
■
■
■
■
Figure 10–2
numbering convention.
Quartus II software.
The anchor point, or origin, in Stratix and Stratix GX devices is in the
bottom-left corner, instead of the top-left corner as in APEX II and
APEX 20K devices.
The anchor point, or origin, of a large block element (e.g., a M-RAM
or DSP block) is also the bottom-left corner.
All numbers are zero-based, meaning the origin at the bottom-left of
the device is X0, Y0.
The I/O pins constitute the first and last rows and columns in the
X-Y coordinates. Therefore, the bottom row of pins resides in
X<number>, Y0, and the first left column of pins resides in X0,
Y<number>.
The sub-location of elements, N, numbering begins at the top.
Therefore, the LEs in an LAB are still numbered from top to bottom,
but start at zero.
<element_name>
_Y
<element_name>
_Y
pin_
<number>
<number>
highlights the new location syntax used for Stratix and
<pin_label>
show the Stratix and Stratix GX architectural element
Location Syntax
_N
<number>
_X
_X
Figure 10–3
<number>
<number>
LAB_X1_Y1
LC_X1_Y1_N0
pin_5
displays the floorplan view in the
Location
Example of Location Syntax
Designates the LAB in
row 1, column 1
Designates the first
LE, N0, in the LAB
located in row 1,
column 1
Pin 5
Altera Corporation
Description
July 2005