EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 419

• Manufacturer Part Number: EP1S20F780I6N
• Description: IC STRATIX FPGA 20K LE 780-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F780I6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 586
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 18460
• # I/os (max): 586
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 18460
• Ram Bits: 1669248
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Figure 3–12. DQ Configuration in Stratix & Stratix GX IOE
Notes to
(1)
(2)
(3)
(4)
Altera Corporation
June 2006
Logic Array
You can use the altdq megafunction to generate the DQ signals.
The OE signal is active low, but the Quartus II software implements this as active high and automatically adds an
inverter before the OE register A
The outclock signal is phase shifted –90° from the system clock.
The shifted DQS signal must be inverted before going to the IOE. The inversion is automatic if you use the altdq
megafunction to generate the DQ signals.
Figure
3–12:
dataout_h
(4)
dataout_l
inclock (from DQS bus)
(2)
datain_h
outclock (3)
OE
datain_l
OE
during compilation.
Latch C
Q
Latch
ENA
TCH
Output Register A
Output Register B
External Memory Interfaces in Stratix & Stratix GX Devices
I
D
LA
OE Register A
DFF
DFF
DFF
D
D
D
neg_reg_out
Q
Q
Q
OE
Note (1)
O
O
Input Register A
Input Register B
Q
Q
DFF
DFF
Stratix Device Handbook, Volume 2
D
D
0
1
I
I
TRI
DQ Pin
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