EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 11

IC STRATIX FPGA 20K LE 780-FBGA

EP1S20F780I6N

Manufacturer Part Number
EP1S20F780I6N
Description
IC STRATIX FPGA 20K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheets

Specifications of EP1S20F780I6N

Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
586
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
18460
# I/os (max)
586
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
18460
Ram Bits
1669248
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1S20F780I6N
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP1S20F780I6N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP1S20F780I6N
Manufacturer:
ALTERA
0
Revision History
Altera Corporation
Chapter
1
September 2004, v3.1
January 2004, v2.2
October 2003, v2.1
April 2004, v3.0
July 2005, v3.2
July 2003, v2.0
Date/Version
This section provides the data sheet specifications for Stratix
They contain feature definitions of the internal architecture,
configuration and JTAG boundary-scan testing information, DC
operating conditions, AC timing parameters, a reference to power
consumption, and ordering information for Stratix devices.
This section contains the following chapters:
The table below shows the revision history for
Chapter 1, Introduction
Chapter 2, Stratix Architecture
Chapter 3, Configuration & Testing
Chapter 4, DC & Switching Characteristics
Chapter 5, Reference & Ordering Information
Minor content changes.
Updated
Main section page numbers changed on first page.
Changed PCI-X to PCI-X 1.0 in
Global change from SignalTap to SignalTap II.
The DSP blocks in
implementation of multipliers that are now “faster than 300 MHz.”
Updated -5 speed grade device information in Table 1-6.
Add -8 speed grade device information.
Format changes throughout chapter.
Section I. Stratix Device
Table 1–6 on page
“Features” on page 1–2
Changes Made
Family Data Sheet
1–5.
“Features” on page
Chapters 1
provide dedicated
1–2.
through 5.
®
Section I–1
devices.

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