EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 605

• Manufacturer Part Number: EP1S20F780I6N
• Description: IC STRATIX FPGA 20K LE 780-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F780I6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 586
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 18460
• # I/os (max): 586
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 18460
• Ram Bits: 1669248
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Altera Corporation
September 2004
Note to
(1)
Table 7–12. Decomposition of a 16-Tap Decimation Filter into Four Polyphase Filters
The output sample is the sum of the results from four polyphase filters: y(n) = y(n)
Table
Output Sample
y(0)
y(0)
y(0)
y(0)
7–12:
0
1
2
3
, y(4)
, y(4)
, y(4)
, y(4)
0
1
2
3
, . . .
, . . .
, . . .
, . . .
(1)
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
where:
This equation implies that the first polyphase filter, h
h(0), h(D), h(2D)…h((P-1)D). The second polyphase filter, h
coefficients h(1), h(1+D), h(1+2D), ..., h(1+(P-1)D). Continuing in this way,
the last polyphase filter, h
h((D - 1) + 2D), ..., h((D - 1) + (P-1)D).
An example helps in the understanding of the polyphase implementation
of decimation. Consider the polyphase representation of a 16-tap low
pass filter with a decimation factor of 4. The output is given by:
Referring to
discarded for n
computed are y(0), y(4), y(8), y(12).
are required to generate the output samples.
Table 7–12
represented by 4 parallel polyphase filters.
polyphase representation of the decimation filter. A demultiplexer at the
input ensures that the input is applied to only one polyphase filter at a
k = 0,1, …, D-1
n = 0,1, …, P-1
P = L/D = length of polyphase filters
L is the length of the filter (selected to be a multiple of D)
D is the decimation factor
h(n) is the original filter impulse response
y n
Coefficients Required
h(2), h(6), h(10), h(14)
h(3), h(7), h(11), h(15)
h(0), h(4), h(8), h(12)
h(1), h(5), h(9), h(13)
=
shows that the overall decimation filter operation can be
i
Figure 7–15 on page
15
=
0
h i x nD i –
0, 4, 8, 12, hence the only values of y(n) that need to be
D-1
(n) has coefficients h(D-1), h((D - 1) + D),
7–26, it is clear that the output, y(n) is
Table 7–12
Polyphase Filter Impulse Response
Stratix Device Handbook, Volume 2
Figure 7–16
shows which coefficients
0
+ y(n)
h
h
h
h
0
1
2
3
0
(n)
(n)
(n)
(n)
1
(n), has coefficients
+ y(n)
shows the
1
(n), has
2
+ y(n)
3.
7–27