ANXS1750FXC3M AMD (ADVANCED MICRO DEVICES), ANXS1750FXC3M Datasheet - Page 62

• Manufacturer Part Number: ANXS1750FXC3M
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ANXS1750FXC3M

• Lead Free Status / RoHS Status: Compliant

3)
4)
5)
6)
62
The processor PLL is powered by V
sor PLL does not lock if V
the processor logic to switch for some period before
PWROK is asserted. V
tion at least 5 µs before PWROK is asserted.
In practice V
planes must be within specification for several milli-
seconds before PWROK is asserted.
After PWROK is asserted, the processor PLL locks to
its operational frequency.
The system clock (SYSCLK/SYSCLK#) must be run-
ning before PWROK is asserted.
When PWROK is asserted, the processor switches
from driving the internal processor clock grid from the
ring oscillator to driving from the PLL. The reference
system clock must be valid at this time. The system
clocks are designed to be running after 3.3V has been
within specification for 3 ms.
PWROK assertion to de-assertion of RESET#.
The duration of RESET# assertion during cold boots is
intended to satisfy the time it takes for the PLL to lock
with a less than 1 ns phase error. The processor PLL
begins to run after PWROK is asserted and the inter-
nal clock grid is switched from the ring oscillator to the
PLL. The PLL lock time may take from hundreds of
nanoseconds to tens of microseconds. It is recom-
mended that the minimum time between PWROK
assertion to the de-assertion of RESET# be at least
1.0 ms. Southbridge enforces a delay of 1.5 to 2.0 ms
between PWRGD (Southbridge version of PWROK)
assertion and NB_RESET# de-assertion.
PWROK must be monotonic and meet the timing
requirements as defined in Table 5-14 "General AC
Characteristics" on page 57. The processor should not
switch between the ring oscillator and the PLL after the
initial assertion of PWROK.
NB_RESET# must be asserted (causing CONNECT to
also assert) before RESET# is de-asserted. In practice
all Southbridge enforces this requirement.
If NB_RESET# does not assert until after RESET# has
de-asserted, the processor misinterprets the CON-
NECT assertion (due to NB_RESET# being asserted)
as the beginning of the SIP (Serial Initialization
Packet) transfer. There must be sufficient overlap in
the resets to ensure that CONNECT is sampled
asserted by the processor before RESET# is de-
asserted.
CCA
, V
31177H
CC_CORE
CCA
CCA
must be within specifica-
, and all other voltage
is not high enough for
CCA
. The proces-
7)
8)
5.10.1.2 Clock Multiplier Selection (FID[3:0])
The chipset samples the FID[3:0] signals in a chipset-spe-
cific manner from the processor and uses this information
to determine the correct SIP. The chipset then sends the
SIP information to the processor for configuration of the
AMD processor system bus for the clock multiplier that
determines the processor frequency indicated by the
FID[3:0] code. The SIP is sent to the processor using the
SIP protocol. This protocol uses the PROCRDY, CON-
NECT, and CLKFWDRST signals, that are synchronous to
SYSCLK.
For more information, see Section 2.3.7 "Frequency ID
Interface Signals" on page 28.
5.10.1.3 Serial Initialization Packet (SIP) Protocol
Refer to AMD Athlon™ Processor System Bus Specifica-
tion (publication ID 21902) for details of the SIP protocol.
5.10.2
Processor and Northbridge Reset Pins
RESET# cannot be asserted to the processor without also
being asserted to the Northbridge. RESET# to the North-
bridge is the same as PCI RESET#. The minimum asser-
tion for PCI RESET# is 1 ms. Southbridge enforces a
minimum assertion of RESET# for the processor, North-
bridge, and PCI of 1.5 to 2.0 ms.
The FID[3:0] signals are valid within 100 ns after
PWROK is asserted. The chipset must not sample the
FID[3:0] signals until they become valid. Refer to the
AMD Athlon™ Processor-Based Motherboard Design
Guide (publication ID 24363) for the specific imple-
mentation and additional circuitry required.
The FID[3:0] signals become valid within 100 ns after
RESET# is asserted. Refer to the AMD Athlon™ Pro-
cessor-Based Motherboard Design Guide (publication
ID 24363) for the specific implementation and addi-
tional circuitry required.
Processor Warm Reset Requirements
AMD Geode™ NX Processors Data Book
Electrical Specifications