ANXS1750FXC3M AMD (ADVANCED MICRO DEVICES), ANXS1750FXC3M Datasheet - Page 61

• Manufacturer Part Number: ANXS1750FXC3M
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ANXS1750FXC3M

• Lead Free Status / RoHS Status: Compliant

Electrical Specifications
5.10
This chapter describes the AMD Geode™ NX processor’s
power-up requirements during system power-up and warm
resets.
5.10.1
5.10.1.1 Signal Sequence and Timing Description
Figure 5-5 shows the relationship between key signals in
the system during a power-up sequence. This figure details
the requirements of the processor.
Note: Figure 5-5 represents several signals generically
The signal timing requirements for Figure 5-5 are as fol-
lows:
1)
AMD Geode™ NX Processors Data Book
RESET# must be asserted before PWROK is
asserted.
The Geode NX processor does not set the correct
clock multiplier if PWROK is asserted prior to a
RESET# assertion. It is recommended that RESET#
be asserted at least 10 ns prior to the assertion of
PWROK.
(Processor Core)
System Clock
by using names not necessarily consistent with
any pin lists or schematics.
V
NB_RESET#
3.3 V Supply
CCA
Signal and Power-Up Requirements
Power-Up Requirements
V
CC_CORE
(for PLL)
RESET#
PWROK
FID[3:0]
(2.5 V)
Figure 5-5. Signal Relationship Requirements During Power-Up Sequence
3
1
5
2
7
6
4
2)
In practice, a Southbridge asserts RESET# millisec-
onds before PWROK is asserted.
All circuit board voltage planes must be within specifi-
cation before PWROK is asserted.
PWROK is an output of the voltage regulation circuit
on the circuit board. PWROK indicates that V
and all other voltage planes in the system are within
specification.
The circuit board is required to delay PWROK asser-
tion for a minimum of three milliseconds from the 3.3V
supply being within specification. This delay ensures
that the system clock (SYSCLK/SYSCLK#) is operat-
ing within specification when PWROK is asserted.
The processor core voltage, V
specification before PWROK is asserted as dictated
by the VID[4:0] pins strapped on the processor pack-
age. Before PWROK assertion, the processor is
clocked by a ring oscillator. Before PWROK is
asserted, the SOFTVID[4:0] outputs of the processor
are not driven to a deterministic value. The processor
drives the SOFTVID[4:0] outputs to the same value as
dictated by the VID[4:0] pins within 20 ns of PWROK
assertion.
8
Warm Reset
Condition
31177H
CC_CORE
, must be within
CC_CORE
61