ANXS1750FXC3M AMD (ADVANCED MICRO DEVICES), ANXS1750FXC3M Datasheet - Page 35

• Manufacturer Part Number: ANXS1750FXC3M
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ANXS1750FXC3M

• Lead Free Status / RoHS Status: Compliant

Power Management
3.1.4
The Probe state is entered when the Northbridge connects
the AMD processor system bus to probe the processor (for
example, to snoop the processor caches) when the proces-
sor is in the Halt or Stop Grant state. When in the Probe
state, the processor responds to a probe cycle in the same
manner as when it is in the Working state. When the probe
has been serviced, the processor returns to the same state
as when it entered the Probe state (Halt or Stop Grant
state). When probe activity is completed the processor only
returns to a low-power state after the Northbridge discon-
nects the AMD processor system bus again.
3.1.5
The FID_Change State is part of the AMD processor sys-
tem bus FID_Change Protocol. During the FID_Change
state the Frequency Identification (FID[4:0]) code that
determines the core frequency of the processor and Volt-
age Identification (VID[4:0]) driven on the SOFTVID[4:0]
pins are transitioned to change the core frequency and
core voltage of the processor. The NX 1750@14W proces-
sor* supports multiple core voltages whereas the
NX 1500@6W and NX 1250@6W processors* support
only
(NX 1250@6W = 1.1V).
Note: The FID[3:0] pins of the processor do not transition
3.1.6
The FID_Change protocol is used by AMD PowerNow!
software to transition the processor from one performance
state to another. The FID_Change protocol is also used for
ACPI 2.0-compliant processor performance state control.
Processor performance states are combinations of proces-
sor core voltage and core frequency. Processor perfor-
mance states are used in embedded systems to optimize
the power consumption of the processor (and therefore
battery powered run-time) based upon processor utiliza-
tion.
Table 5-4 "Voltage and Frequency Combinations" on page
49. specifies the valid voltage and frequency combinations
supported by the processor based upon the maximum core
frequency and the maximum nominal core voltage.
The core frequency multiplier is determined by a 5-bit Fre-
quency ID (FID) code (MSR C001_0041h[4:0]). The core
voltage is determined by a 5-bit Voltage ID (VID) code
(MSR C001_0041h[12:8]).
Before PWROK is asserted to the processor, the VID[4:0]
outputs of the processor dictate the core voltage level of
the processor.
*The AMD Geode™ NX 1750@14W processor operates at 1.4 GHz, the NX 1500@6W processor operates at 1.0 GHz, and the NX 1250@6W processor operates
at 667 MHz. Model numbers reflect performance as described here: http://www.amd.com/connectivitysolutions/geodenxbenchmark.
AMD Geode™ NX Processors Data Book
one
as part of the FID_Change protocol.
Probe State
FID_Change State
Processor Performance States and the
FID_Change Protocol
core
voltage
(NX 1500@6W
=
1.0V)
After PWROK is asserted, the core voltage of the proces-
sor is dictated by the SOFTVID[4:0] outputs. The SOFT-
VID[4:0] outputs of the processor are not driven to a
deterministic value until after PWROK is asserted to the
processor. The circuit board therefore must provide a ‘VID
Multiplexer’ to drive the VID[4:0] outputs to the DC/DC con-
verter for the core voltage of the processor before PWROK
is asserted and drive the SOFTVID[4:0] outputs to the
DC/DC converter after PWROK is asserted.
The FID[3:0] signals are valid within 100 ns after PWROK
is asserted. The chipset must not sample the FID[3:0] sig-
nals until they become valid. For warm reset, the FID[3:0]
signals become valid within 100 ns after RESET# is
asserted. For signal timing requirements refer to Section
5.10 "Signal and Power-Up Requirements" on page 61.
After RESET# is de-asserted, the FID[3:0] outputs are not
used to transmit FID information for subsequent software
controlled changes in the operating frequency of the pro-
cessor.
Processor performance state transitions are required to
occur as two separate transitions. The order of these tran-
sitions depends on whether the transition is to a higher or
lower performance state.
When transitioning from a lower performance state to a
higher performance state the order of the transitions is:
1)
2)
When transitioning from a high performance state to a
lower performance state the order of the transitions is:
1)
2)
The processor provides two MSRs to support the
FID_Change
C001_0041h)
C001_0042h). For a definition of these MSRs and their
use, refer to the BIOS Requirements for AMD PowerNow™
Technology Application Note (publication ID 25264)
The FID_Change protocol is used to transition to the
higher voltage, while keeping the frequency fixed at
the current setting.
The FID_Change protocol is then used to transition to
the higher frequency, while keeping the voltage fixed at
the higher setting.
The FID_Change protocol is used to transition to the
lower frequency, while keeping the voltage fixed at its
current setting.
The FID_Change protocol is then used to transition to
the lower voltage, while keeping the frequency fixed at
the lower setting.
protocol:
and
the
the
31177H
FidVidStatus
FidVidCtl
MSR
MSR
(MSR
(MSR
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