ANXS1750FXC3M AMD (ADVANCED MICRO DEVICES), ANXS1750FXC3M Datasheet - Page 38

• Manufacturer Part Number: ANXS1750FXC3M
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ANXS1750FXC3M

• Lead Free Status / RoHS Status: Compliant

3.2
Significant power savings of the processor only occur if the
processor is disconnected from the system bus by the
Northbridge while in the Halt or Stop Grant state. The
Northbridge can optionally initiate a bus disconnect upon
the receipt of a Halt or Stop Grant special cycle. The option
of disconnecting is controlled by an enable bit in the North-
bridge. If the Northbridge requires the processor to service
a probe after the system bus has been disconnected, it
must first initiate a system bus connect.
3.2.1
In addition to the legacy STPCLK# signal and the Halt and
Stop Grant special cycles, the AMD processor system bus
connect protocol includes the CONNECT, PROCRDY, and
CLKFWDRST signals and a Connect special cycle.
AMD processor system bus disconnects are initiated by
the Northbridge in response to the receipt of a Halt, Stop
Grant, or FID_Change special cycle. Reconnect is initiated
by the processor in response to an interrupt for Halt,
STPCLK# de-assertion, or completion of a FID_Change
transition. Reconnect is initiated by the Northbridge to
probe the processor.The Northbridge contains BIOS pro-
grammable registers to enable the system bus disconnect
in response to Halt and Stop Grant special cycles. When
the Northbridge receives the Halt or Stop Grant special
cycle from the processor and, if there are no outstanding
probes or data movements, the Northbridge de-asserts
CONNECT a minimum of eight SYSCLK periods after the
last command sent to the processor. The processor
detects the de-assertion of CONNECT on a rising edge of
SYSCLK and de-asserts PROCRDY to the Northbridge. In
38
AMD Processor
CLKFWDRST
System Bus
PROCRDY
CONNECT
Figure 3-3. AMD Processor System Bus Disconnect Sequence in the Stop Grant State
Connect and Disconnect Protocol
Connect Protocol
STPCLK#
PCI Bus
31177H
Stop Grant
return, the Northbridge asserts CLKFWDRST in anticipa-
tion of reestablishing a connection at some later point.
Note: The Northbridge must disconnect the processor
The processor can receive an interrupt after it sends a Halt
special cycle, or STPCLK# de-assertion after it sends a
Stop Grant special cycle to the Northbridge but before the
disconnect actually occurs. In this case, the processor
sends the Connect special cycle to the Northbridge, rather
than continuing with the disconnect sequence. In response
to the Connect special cycle, the Northbridge cancels the
disconnect request.
The system is required to assert the CONNECT signal
before returning the C-bit for the connect special cycle
(assuming CONNECT has been de-asserted).
For more information, see the AMD Athlon™ Processor
System Bus Specification (publication ID 21902)for the def-
inition of the C-bit and the Connect special cycle.
Figure 3-3 shows STPCLK# assertion resulting in the pro-
cessor in the Stop Grant state and the AMD processor sys-
tem bus disconnected.
from the AMD processor system bus before issu-
ing the Stop Grant special cycle to the PCI bus or
passing the Stop Grant special cycle to the South-
bridge for systems that connect to the Southbridge
with HyperTransport™ technology.
In response to Halt special cycles, the Northbridge
passes the Halt special cycle to the PCI bus or
Southbridge immediately.
AMD Geode™ NX Processors Data Book
Stop Grant
Power Management