ANXS1750FXC3M AMD (ADVANCED MICRO DEVICES), ANXS1750FXC3M Datasheet - Page 29

• Manufacturer Part Number: ANXS1750FXC3M
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ANXS1750FXC3M

• Lead Free Status / RoHS Status: Compliant

Signal Definitions
2.3.9
AMD Geode™ NX Processors Data Book
Signal Name
SOFTVID[4:0]
VID[4:0]
Voltage Control Interface Signals (continued)
J7, L7, L5,
H10, H8,
Pin No.
H6, K8,
L3, L1
F8
Port
O
O
Description
Soft Voltage ID/Voltage ID Mux. AMD PowerNow!™ technology
can use the FID_Change protocol described in Section 4.1 on
page 9 to transition the SOFTVID[4:0] outputs and therefore
V
Note:
The VID[4:0] (Voltage ID) and SOFTVID[4:0] (Software driven Volt-
age ID) outputs are used by the DC/DC power converter to select
the processor core voltage. The VID[4:0] pins are shorted to ground
or left unconnected on the package and must be pulled up on the
circuit board. The SOFTVID[4:0] pins are open-drain and 2.5V toler-
ant.
Refer to the VCC_2.5V Generation Circuit found in the Motherboard
Required Circuits section of the AMD Athlon™ Processor-Based
Motherboard Design Guide (publication ID 24363) for the required
supporting circuitry.
The circuit board is required to implement a VID multiplexer to
select a deterministic voltage for the processor at power-up before
the PWROK input is asserted. Before PWROK is asserted, the VID
multiplexer drives the VID value from VID[4:0] pins to the DC/DC
converter for V
plexer drives the VID value from the SOFTVID[4:0] pins to the
DC/DC converter for V
AMD Athlon™ Processor-Based Motherboard Design Guide (publi-
cation ID 24363) and the AMD Geode™ NX Processors Addendum
to AMD Athlon™ Processor-Based Motherboard Design Guide
(publication ID 31860) for the recommended VID multiplexer circuit.
The SOFTVID[4:0] pins are driven by the processor to select the
maximum V
VID field of the FidVidStatus MSR (MSR C001_0042h) within 20 ns
of
SOFTVID[4:0] outputs are not driven to a deterministic value. The
SOFTVID[4:0] outputs must be used to select V
PWROK is asserted. Any time the RESET# input is asserted, the
SOFTVID[4:0] pins will be driven to select the maximum voltage.
Note:
AMD PowerNow! technology can use the FID_Change protocol
described in Section 3.1 "Power Management States" on page 33 to
transition the SOFTVID[4:0] outputs and therefore V
part of processor performance state transitions.
The VID codes used by the processor are defined in Table 2-3
"SOFTVID[4:0] and VID[4:0] Code to Voltage Definition" on page
30.
*The AMD Geode™ NX 1750@14W processor operates at 1.4 GHz, the NX 1500@6W
processor operates at 1.0 GHz, and the NX 1250@6W processor operates at 667 MHz.
Model numbers reflect performance as described here:
http://www.amd.com/connectivitysolutions/geodenxbenchmark.
CC_CORE
PWROK
The NX 1750@14W processor* supports multiple core volt-
ages whereas the NX 1500@6W and NX 1250@6W pro-
cessors* support only one core voltage (NX 1500@6W =
1.0V) (NX 1250@6W = 1.1V).
The Start-up VID and Maximum VID fields of the FidVidSta-
tus MSR report the same value that corresponds to the
nominal voltage that the processor requires to operate at
maximum frequency.
as part of processor performance state transitions.
CC_CORE
CC_CORE
assertion.
of the processor as reported by the Maximum
. After PWROK is asserted, the VID multi-
CC_CORE
Before
of the processor. Refer to the
PWROK
31177H
is
asserted,
CC_CORE
CC_CORE
after
the
as
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