ANXS1750FXC3M AMD (ADVANCED MICRO DEVICES), ANXS1750FXC3M Datasheet - Page 26

• Manufacturer Part Number: ANXS1750FXC3M
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ANXS1750FXC3M

• Lead Free Status / RoHS Status: Compliant

2.3.3
2.3.4
26
Signal Name
INIT#
INTR
NMI
A20M#
SMI#
FLUSH#
Signal Name
VREF_SYS
SDATA[63:0]#
SDATAINCLK[3:0]#
SDATAOUTCLK[3:0]
SDATAINVALID#
SDATAOUTVALID#
Southbridge Interface Signals (continued)
AMD Processor System Bus Interface Signals
31177H
See Table
E15, E27,
C11, A33,
J35, W33
page 23
Pin No.
Pin No.
2-2 on
AN33
AE35
AL31
C37,
AN3
AE1
AN5
AJ3
AL1
AL3
W5
Port
Port
B
O
I
I
I
I
I
I
I
I
I
I
Description
Interrupt Integer Registers. When asserted, INIT# resets the inte-
ger registers without affecting the floating point registers or the inter-
nal caches. Execution starts at 0FFFF_FFF0h
Interrupt. An input from the system that causes the processor to
start an interrupt acknowledge transaction that fetches the 8-bit
interrupt vector and starts execution at that location.
Non-Maskable Interrupt. An input from the system that causes a
non-maskable interrupt.
Address Bit 20. An input from the system used to simulate address
wrap-around in the 20-bit 8086.
System Management Interrupt. An input that causes the proces-
sor to enter the system management mode.
Flush. FLUSH# must be tied to V
a debug connector is implemented, FLUSH# is routed to the debug
connector.
Description
System Bus Voltage Reference. This input drives the threshold
voltage for the AMD processor system bus input receivers. The
value of VREF_SYS is system specific. In addition, to minimize
V
capacitors. For more information, see the AMD Athlon™ Processor-
Based Motherboard Design Guide (publication ID 24363) and AMD
Geode™ NX Processors Addendum to AMD Athlon™ Processor-
Based Motherboard Design Guide (publication ID 31860).
System Data Bus. Bidirectional interface to and from the processor
and system for data movement. Data is skewed-aligned with either
the SDATAINCLK[3:0]# or SDATAOUTCLK[3:0]# signal. Both rising
and falling edges are used to transfer data.
System Data Input Clock. The single-ended forwarded clock
driven by the system to transfer data on SDATA[63:0]#. Each 16-bit
data word is skewed-aligned with this clock. Both rising and falling
edges are used to transfer data.
System Data Output Clock. The single-ended forwarded clock
driven by the system to transfer data on SDATA[63:0]#. Each 16-bit
data word is skewed-aligned with this clock. Both rising and falling
edges are used to transfer data.
System Data Input Valid. This input is driven by the system and
controls the flow of data into the processor. SDATAINVALID# can
be used to introduce an arbitrary number of cycles between octa-
words into the processor.
System Data Output Valid. This input is driven by the system and
controls the flow of data from the processor. SDATAOUTVALID#
can be used to introduce an arbitrary number of cycles between
quadwords into the processor.
CC_CORE
noise rejection from VREF_SYS, include decoupling
AMD Geode™ NX Processors Data Book
CC_CORE
with a pull-up resistor. If
Signal Definitions