ANXS1750FXC3M AMD (ADVANCED MICRO DEVICES), ANXS1750FXC3M Datasheet - Page 58
ANXS1750FXC3M
Manufacturer Part Number
ANXS1750FXC3M
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet
1.ANXS1750FXC3M.pdf
(72 pages)
Specifications of ANXS1750FXC3M
Lead Free Status / RoHS Status
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5.7
Figure 5-4 is a test circuit that may be used on automated
test equipment (ATE) to test for validity on open-drain pins.
58
Figure 5-4. General ATE Open-Drain Test Circuit
Note 1. V
Note 2. I
Open-drain Pin
Open-Drain Test Circuit
V
I
OL
OL
Termination
Termination
= –6 mA for VID and FID pins
= –9 mA for APIC pins
= 1.2 V for VID and FID pins
= 1.0 V for APIC pins
I
OL
31177H
= Output Current (Note 2)
V
Termination
50 Ω ±3%
(Note 1)
5.8
Table 5-15 shows the time required for the PLL of the pro-
cessor to lock at the new frequency specified in a
FID_Change transition.
Software must program the SGTC field of the FidVidCtl
MSR (MSR C001_0041h) to produce a FID_Change dura-
tion equal to or greater than the FID_Change induced PLL
lock time.
For more information about the FID_Change protocol, see
Section 3.1 "Power Management States" on page 33.
Table 5-15. FID_Change Induced PLL Lock Time
Parameter
FID_Change Induced PLL Lock
Time
FID_Change Induced PLL Lock
Time
AMD Geode™ NX Processors Data Book
Electrical Specifications
Max
50
Units
µs
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