MT49H32M9FM-33 IT Micron Technology Inc, MT49H32M9FM-33 IT Datasheet - Page 40

• Manufacturer Part Number: MT49H32M9FM-33 IT
• Manufacturer: Micron Technology Inc
• Type: RLDRAMr

Specifications of MT49H32M9FM-33 IT

• Organization: 32Mx9
• Density: 288Mb
• Address Bus: 22b
• Maximum Clock Rate: 300MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: uBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 609mA
• Pin Count: 144
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Not Compliant

READ
Figure 14:
PDF: 09005aef80a41b46/Source: 09005aef809f284b
RLDRAM_II_CIO_Core.fm - Rev. D 12/10 EN
READ Command
Read accesses are initiated with a READ command, as shown in Figure 14. Addresses are
provided with the READ command.
During READ bursts, the memory device drives the read data so it is edge-aligned with
the QKx signals. After a programmable READ latency, data is available at the outputs.
One half clock cycle prior to valid data on the read bus, the data valid signal, QVLD, tran-
sitions from LOW to HIGH. QVLD is also edge-aligned with the QKx signals.
The skew between QK and the crossing point of CK is specified as
skew between QK0 and the last valid data edge generated at the DQ signals associated
with QK0 (
for the x18 configuration).
generated at the DQ signals associated with QK1 (
the x36 and DQ9–DQ17 for the x18 configuration).
edge and is not cumulative over time.
differential pair and any output data edge.
After completion of a burst, assuming no other commands have been initiated, output
data (DQ) will go High-Z. The QVLD signal transitions LOW on the last bit of the READ
burst. Note that if CK/CK# violates the V
ring, QVLD will remain HIGH until a dummy READ command is issued. The QK clocks
are free-running and will continue to cycle after the read burst is complete. Back-to-
back READ commands are possible, producing a continuous flow of output data.
The data valid window is derived from each QK transition and is defined as:
t
Any READ burst may be followed by a subsequent WRITE command. Figure 26 on
page 52 illustrate the timing requirements for a READ followed by a WRITE. Some
systems having long line lengths or severe skews may need additional idle cycles
inserted between READ and WRITE commands to prevent data bus contention.
QHP - (
ADDRESS
ADDRESS
BANK
REF#
WE#
CK#
CS#
CK
288Mb: x9, x18, x36 2.5V V
t
QKQ [MAX] + |
t
QKQ0 is referenced to DQ0–DQ17 for the x36 configuration and DQ0–DQ8
DON’T CARE
BA
A
t
QKQ [MIN]|). See Figures 27–29 for illustration.
t
QKQ1 is the skew between QK1 and the last valid data edge
40
t
QKQ is defined as the skew between either QK
Micron Technology, Inc., reserves the right to change products or specifications without notice.
ID
(DC)
EXT
, 1.8V V
specification while a READ burst is occur-
t
QKQ1 is referenced to DQ18–DQ35 for
t
QKQx is derived at each QKx clock
DD
, HSTL, CIO, RLDRAM II
©2004 Micron Technology, Inc. All rights reserved.
t
CKQK.
Commands
t
QKQ0 is the