MT49H32M9FM-33 IT Micron Technology Inc, MT49H32M9FM-33 IT Datasheet - Page 17

• Manufacturer Part Number: MT49H32M9FM-33 IT
• Manufacturer: Micron Technology Inc
• Type: RLDRAMr

Specifications of MT49H32M9FM-33 IT

• Organization: 32Mx9
• Density: 288Mb
• Address Bus: 22b
• Maximum Clock Rate: 300MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: uBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 609mA
• Pin Count: 144
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Not Compliant

Electrical Specifications – I
Table 5:
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_II_CIO_D2.fm - Rev. M 12/10 EN
Standby current
Active standby
current
Operational
current
Operational
current
Operational
current
Burst refresh
current
Distributed
refresh current
Operating burst
write current
example
Operating burst
write current
example
Operating burst
write current
example
Operating burst
read current
example
Operating burst
read current
example
Description
I
Notes appear on page 19
DD
Operating Conditions and Maximum Limits – Rev. A
t
CS# = 1; No commands; Bank address
incremented and half address/data change
once every 4 clock cycles
BL = 2; Sequential bank access; Bank transitions
once every
every
continuous data during WRITE commands
BL = 4; Sequential bank access; Bank transitions
once every
every
Continuous data during WRITE commands
BL = 8; Sequential bank access; Bank transitions
once every
every
continuous data during WRITE commands
Eight-bank cyclic refresh; Continuous address/
data; Command bus remains in refresh for all
eight banks
Single-bank refresh; Sequential bank access;
Half address transitions once every
continuous data
BL = 2; Cyclic bank access; Half of address bits
change every clock cycle; Continuous data;
measurement is taken during continuous
WRITE
BL = 4; Cyclic bank access; Half of address bits
change every 2 clock cycles; Continuous data;
Measurement is taken during continuous
WRITE
BL = 8; Cyclic bank access; Half of address bits
change every 4 clock cycles; continuous data;
Measurement is taken during continuous
WRITE
BL = 2; Cyclic bank access; Half of address bits
change every clock cycle; Measurement is taken
during continuous READ
BL = 4; Cyclic bank access; Half of address bits
change every 2 clock cycles; Measurement is
taken during continuous READ
CK = idle; All banks idle; No inputs toggling
t
t
t
RC; Read followed by write sequence;
RC; Read followed by write sequence;
RC; Read followed by write sequence;
t
t
t
RC; Half address transitions once
RC; Half address transitions once
RC; half address transitions once
288Mb: x9, x18, x36 2.5V V
Condition
DD
t
RC,
17
I
I
I
I
I
I
I
DD2R
DD4R
Micron Technology, Inc., reserves the right to change products or specifications without notice.
I
I
REF1
REF2
I
DD1
DD2
DD3
I
I
SB1
SB2
I
I
I
I
DD2W
DD4W
DD8W
I
I
I
DD2R
DD4R
I
I
REF1
REF2
DD1
DD2
DD3
SB1
SB2
I
I
I
I
I
I
I
I
I
I
DD2W
DD4W
DD8W
I
I
I
DD2W
DD4W
DD8W
DD2R
DD4R
I
I
REF1
REF2
EXT
DD1
DD2
DD3
SB1
SB2
Symbol
(V
(V
(V
(V
(V
(V
(V
(V
(V
x9/x18
x9/x18
x9/x18
(V
(V
(V
(V
(V
(V
(V
DD
DD
(V
(V
DD
DD
DD
(V
(V
(V
DD
DD
DD
DD
(V
(V
, 1.8V V
(V
(V
(V
DD
DD
(V
(V
DD
DD
DD
DD
DD
(V
(V
(V
(V
(V
DD
DD
) x9/x18
) x9/x18
(V
(V
(V
DD
DD
DD
) x9/x18
) x9/x18
) x9/x18
) x9/x18
) x9/x18
EXT
EXT
) x9/x18
) x9/x18
EXT
EXT
EXT
EXT
EXT
) x36
) x36
EXT
EXT
) x36
) x36
) x36
) x36
) x36
EXT
EXT
EXT
DD
DD
DD
) x36
) x36
) x36
)
) x36
Electrical Specifications – I
)
)
X
)
)
)
)
)
)
)
)
)
)
)
36
)
)
DD
288
288
348
374
362
418
408
785
785
133
325
326
970
990
100
779
882
668
860
880
100
680
730
-25
n/a
n/a
48
48
26
26
41
48
55
48
88
60
88
, HSTL, CIO, RLDRAM II
©2003 Micron Technology, Inc. All rights reserved.
233
233
305
343
319
389
368
615
615
111
267
281
819
914
609
790
525
735
795
525
660
-33
n/a
n/a
48
48
26
26
36
42
48
42
90
77
51
90
77
189
189
255
292
269
339
286
430
430
105
221
227
597
676
439
567
364
525
565
380
455
n/a
n/a
48
48
26
26
36
42
48
42
69
63
40
69
63
-5
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
DD