ADV7196AKSZ Analog Devices Inc, ADV7196AKSZ Datasheet - Page 9

• Manufacturer Part Number: ADV7196AKSZ
• Manufacturer: Analog Devices Inc

Specifications of ADV7196AKSZ

• Adc/dac Resolution: 11b
• Screening Level: Commercial
• Package Type: MQFP
• Pin Count: 52
• Lead Free Status / RoHS Status: Compliant

Pin
1, 12
2–11
13, 52
14–23
24, 35
25
26, 33
27
28
29
30
31
32
34
36
37
38
39
40
41
42–51
Mnemonic
V
Y0–Y9
GND
Cr0–Cr9
V
CLKIN
AGND
DV
VSYNC/
TSYNC
HSYNC/
SYNC
SCL
SDA
DAC C
DAC A
DAC B
COMP
R
V
RESET
ALSB
Cb/Cr9–0
DD
AA
SET
REF
Input/Output
P
I
G
I
P
I
G
I
I
I
I
I/O
O
O
O
O
I
I/O
I
I
I
PIN FUNCTION DESCRIPTIONS
Function
Digital Power Supply
10-Bit Progressive Scan/HDTV Input Port for Y Data. Input for G data when
RGB data is input.
Digital Ground
1
In 4:2:2 mode this input port is not used. Input port for R data when RGB data
is input.
Analog Power Supply
Pixel Clock Input. Requires a 27 MHz reference clock for standard operation in
Progressive Scan Mode or a 74.25 MHz (74.1758 MHz) reference clock in
HDTV mode.
Analog Ground
Video Blanking Control Signal Input
VSYNC, Vertical Sync Control Signal Input or TSYNC Input Control Signal in
Async Timing Mode
HSYNC, Horizontal
Async Timing Mode
MPU Port Serial Interface Clock Input
MPU Port Serial Data Input/Output
Color Component Analog Output of Input Data on Cb/Cr9–0 Input Pins
Y Analog Output
Color Component Analog Output of Input Data on Cr9–Cr0 Input Pins
Compensation Pin for DACs. Connect 0.1 µF capacitor from COMP pin to V
A 2470 Ω resistor (for input ranges 64–940 and 64–960; output standards
EIA-770.1–EIA-770.3) must be connected from this pin to ground and is used to
control the amplitudes of the DAC outputs. For input ranges 0–1023 (output
standards RS-170, RS-343A) the R
Optional External Voltage Reference Input for DACs or Voltage Reference
Output (1.235 V)
This input resets the on-chip timing generator and sets the ADV7196A into
Default Register setting. Reset is an active low signal.
TTL Address Input. This signal sets up the LSB of the MPU address. When this
pin is tied high, the I
When this pin is tied low, the input bandwidth on the I
1
multiplexed CrCb data must be input on these pins. Input port for B data when
RGB is input.
0-Bit Progressive Scan/HDTV Input Port for Color Data in 4:4:4 Input Mode.
0-Bit Progressive Scan/HDTV Input Port for Color Data. In 4:2:2 mode the
2
Sync Control Signal Input or SYNC Input Control Signal in
C filter is activated which reduces noise on the I
SET
value must be 2820 Ω.
2
C interface is increased.
ADV7196A
2
C interface.
AA
.