ADV7196AKSZ Analog Devices Inc, ADV7196AKSZ Datasheet - Page 30

• Manufacturer Part Number: ADV7196AKSZ
• Manufacturer: Analog Devices Inc

Specifications of ADV7196AKSZ

• Adc/dac Resolution: 11b
• Screening Level: Commercial
• Package Type: MQFP
• Pin Count: 52
• Lead Free Status / RoHS Status: Compliant

ADV7196A
DAC TERMINATION AND LAYOUT CONSIDERATIONS
Voltage Reference
The ADV7196A contains an on-board voltage reference. The
V
when the internal V
can be used with an external V
Resistor R
is used to control the full-scale output current and therefore the
DAC voltage output levels. For full-scale output R
a value of 2470 Ω. R
range of 0–1023 is selected the value of R
The ADV7196A has three analog outputs, corresponding to Y, Pr,
Pb video signals. The DACs must be used with external buffer circuits
in order to provide sufficient current to drive an output device.
Suitable op amps are the AD8009, AD8002, AD8001, or AD8057.
To calculate the output full-scale current and voltage the follow-
ing equations should be used:
where:
k = 5.66 [for input ranges 64–940, 64–960, output standards
k = 6.46 [for input ranges 0–1023, output standard RS–170/343A]
V
REF
REF
EIA770.1–3]
pin is normally terminated to V
= 1.235 V
SET
is connected between the R
REF
I
LOAD
V
OUT
UNUSED
INPUTS
SHOULD BE
GROUNDED
OUT
is used. Alternatively, the ADV7196A
V
DD
= [V
27MHz, 74.25MHz OR
has a value of 300 Ω. When an input
4.7k
74.1758MHz CLOCK
4.7 F
6.3V
= I
OUT
REF
REF
(AD589).
AA
k]/R
R
through a 0.1 µF capacitor
LOAD
SET
V
SET
DD
SET
4.7k
pin and AGND and
must be 2820 Ω.
Cb/Cr0–Cb/Cr9
Cr0–Cr9
Y0–Y9
HSYNC/SYNC
VSYNC/TSYNC
DV
RESET
CLKIN
COMP
SET
ALSB
V
AA
0.1 F
must have
ADV7196A
AGND
V
AA
POWER SUPPLY DECOUPLING
FOR EACH POWER SUPPLY GROUP
26, 33
24, 35
GND
V
DAC A
DAC B
DAC C
DD
V
R
SCL
SDA
13, 52
1, 12
REF
SET
10nF
PC BOARD LAYOUT CONSIDERATIONS
The ADV7196A is optimally designed for lowest noise performance,
both radiated and conducted noise. To complement the excellent
noise performance of the ADV7196A, it is imperative that great
care be given to the PC board layout.
The layout should be optimized for lowest noise on the ADV7196A
power and ground lines. This can be achieved by shielding the
digital inputs and providing good decoupling. The lead length
between groups of V
should be kept as short as possible to minimized inductive ringing.
It is recommended that a four-layer printed circuit board is used.
With power and ground planes separating the layer of the signal
carrying traces of the components and solder side layer. Placement
of components should consider to separate noisy circuits, such
as crystal clocks, high-speed logic circuitry and analog circuitry.
There should be a separate analog ground plane (AGND) and
a separate digital ground plane (GND).
Power planes should encompass a digital power plane (V
a analog power plane (V
the DACs and all associated circuitry, and the V
The digital power plane should contain all logic circuitry. The analog
and digital power planes should be individually connected to the
common power plane at one single point through a suitable filter-
ing device, such as a ferrite bead.
10nF
300
300
300
2.47k
2.82k
0.1 F
100
100
OR
0.1 F
Y OUTPUT
Pr (V) OUTPUT
Pb (U) OUTPUT
V
AA
V
AA
DD
AA
V
5k
DD
and AGND and V
). The analog power plane should contain
V
DD
5k
MPU BUS
DD
and DGND pins
REF
circuitry.
DD
) and