ADV7196AKSZ Analog Devices Inc, ADV7196AKSZ Datasheet - Page 17

• Manufacturer Part Number: ADV7196AKSZ
• Manufacturer: Analog Devices Inc

Specifications of ADV7196AKSZ

• Adc/dac Resolution: 11b
• Screening Level: Commercial
• Package Type: MQFP
• Pin Count: 52
• Lead Free Status / RoHS Status: Compliant

MODE REGISTER 2
MR1 (MR27–MR20)
(Address (SR4–SR0) = 02H)
Figure 22 shows the various operations under the control of Mode
Register 2.
MR2 BIT DESCRIPTION
Y Delay (MR20–MR22)
This control bit delays the Y signal with respect to the falling edge
of the horizontal sync signal by up to four pixel clock cycles.
Figure 21 demonstrates this facility
Color Delay (MR23–MR25)
This control allows delay of the color signals with respect to the
falling edge of the horizontal sync signal by up to four pixel clock
cycles. Figure 21 demonstrates this facility
CGMS Enable (MR26)
When this bit is set to “1,” CGMS data is inserted on Line 41 in
525p mode. The CGMS conforms: to CGMS-A EIA-J CPR1204-1,
Transfer Method of Video ID information using vertical blanking
interval (525p System), March 1998 and IEC61880, 1998, video
systems (525/60)—video and accompanied data using the vertical
blanking interval—analogue interface.
MR27
0
1
CGMS CRC
MR27
DISABLED
ENABLED
.
MR26
0
1
CGMS ENABLE
.
MR26
DISABLED
ENABLED
MR25
MR25 MR24 MR23
0
0
0
0
1
0
0
1
1
0
MR24
COLOR DELAY
0
1
0
1
0
The CGMS data bits are programmed into the CGMS Data
Registers 0–2. For more information refer to CGMS Data
Registers section
CGMS CRC (MR27)
This bit enables the automatic Cyclic Redundancy Check when
CGMS is enabled.
MR23
PrPb DELAY
0 PCLK
1 PCLK
2 PCLK
3 PCLK
4 PCLK
Y DELAY
MR22
MR22 MR21 MR20
0
0
0
0
1
.
NO DELAY
NO DELAY
0
0
1
1
0
MR21
Y DELAY
MAX DELAY
0
1
0
1
0
MAX DELAY
MR20
0 PCLK
1 PCLK
2 PCLK
3 PCLK
4 PCLK
ADV7196A
Y OUTPUT
PrPb OUTPUTS