ADV7196AKSZ Analog Devices Inc, ADV7196AKSZ Datasheet - Page 29

ADV7196AKSZ

Manufacturer Part Number
ADV7196AKSZ
Description
Manufacturer
Analog Devices Inc
Datasheet

Specifications of ADV7196AKSZ

Adc/dac Resolution
11b
Screening Level
Commercial
Package Type
MQFP
Pin Count
52
Lead Free Status / RoHS Status
Compliant
MODE REGISTER 4
MR4 (MR47–MR40)
(Address (SR4–SR0) = 04H)
Figure 55 shows the various operations under the control of Mode
Register 4.
MR4 BIT DESCRIPTION
Timing Reset (MR40)
Toggling MR40 from low to high and low again resets the inter-
nal horizontal and vertical timing counters
MODE REGISTER 5
MR5 (MR57–MR50)
(Address (SR4–SR0) = 05H)
Figure 56 shows the various operations under the control of Mode
Register 5.
MR5 BIT DESCRIPTION
Reserved (MR50)
These bit is reserved for the revision code
RGB Mode (MR51)
When RGB mode is enabled (MR51 = “1”) the ADV7196A accepts
unsigned binary RGB data at its input port. This control is also
available in Async Timing Mode
Sync on PrPb (MR52)
By default the color component output signals Pr, Pb do not contain
any horizontal sync pulses. If required they can be inserted when
MR52 = “1.” This control is not available in RGB mode
MR57
MR47
.
MR56
MR46
ZERO MUST BE
WRITTEN TO
.
MR57–MR54
THESE BITS
.
MR55
MR45
ZERO MUST BE
WRITTEN TO
MR47–MR41
THESE BITS
.
MR54
MR44
MR53
0
1
COLOR OUTPUT
DAC B = Pr
DAC C = Pr
SWAP
MR53
MR43
Color Output Swap (MR53)
By default DAC B is configured as the Pr output and DAC C as
the Pb output. In setting this bit to “1” the DAC outputs can be
swapped around so that DAC B outputs Pb and DAC C outputs
Pr. Table X demonstrates this in more detail.
Reserved (MR54–MR57)
“0” must be written to these bits.
In 4:4:4 Input Mod
Color Data
Input on Pins
Cr9–0
Cb/Cr9–0
Cr9–0
Cb/Cr9–0
In 4:2:2 Input Mod
Color Data
Input on Pins
Cr9–0
Cb/Cr9–0
Cb/Cr9–0
MR52
0
1
Table X. Relationship Between Input Pixel Port, MR53
and DAC B, DAC C Outputs
SYNC ON PrPb
MR52
MR42
DISABLE
ENABLE
MR51
0
1
RGB MODE
MR51
MR41
DISABLE
ENABLE
e
e
MR40
REVISION CODE
RESERVED FOR
TIMING RESET
MR50
MR40
MR50
MR53
0
0
1
1
MR53
0 or 1
0
1
ADV7196A
Analog Output
Signal
DAC B
DAC C
DAC C
DAC
Analog Output
Signal
Not Operational
DAC C (Pb)
DAC C (Pr)
B

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