ADV7196AKSZ Analog Devices Inc, ADV7196AKSZ Datasheet - Page 16

• Manufacturer Part Number: ADV7196AKSZ
• Manufacturer: Analog Devices Inc

Specifications of ADV7196AKSZ

• Adc/dac Resolution: 11b
• Screening Level: Commercial
• Package Type: MQFP
• Pin Count: 52
• Lead Free Status / RoHS Status: Compliant

MODE REGISTER 1
MR1 (MR17–MR10)
(Address (SR4–SR0) = 01H)
Figure 20 shows the various operations under the control of Mode
Register 1.
MR1 BIT DESCRIPTION
Pixel Data Enable (MR10)
When this bit is set to “0,” the pixel data input to the ADV7196A
is blanked such that a black screen is output from the DACs. When
this bit is set to “1,” pixel data is accepted at the input pins and
the ADV7196A outputs the standard set in “Output Standard
Selection” (MR01–00). This bit must be set to “1” to enable out-
put of the test pattern signals.
Input Format (MR11)
It is possible to input data in 4:2:2 format or at 4:4:4 format at
27 MHz.
Test Pattern Enable (MR12)
Enables or disables the internal test pattern generator.
Test Pattern Hatch/Frame (MR13)
If this bit is set to “0,” a cross-hatch test pattern is output from the
ADV7196A (for example, in SMPTE293M 11 horizontal and 11
vertical white lines, four pixels wide are displayed against a black
background). The cross-hatch test pattern can be used to test
monitor convergence.
If this bit is set to “1,” a uniform colored frame/field test pattern
is output from the ADV7196A.
The color of the lines or the frame/field is by default white but can
be programmed to be any color using the Color Y, Color Cr,
Color Cb registers.
ADV7196A
MR17
0
1
SHARPNESS
FILTER
MR17
DISABLED
ENABLED
MR16 MR15
0
0
1
1
UNDERSHOOT
0
1
0
1
LIMITER
MR16
DISABLED
–11IRE
–6IRE
–1.5IRE
MR15
MR14
0
1
VBI OPEN
MR14
DISABLED
ENABLED
MR13
0
1
TEST PATTERN
HATCH/FRAME
VBI Open (MR14)
This bit enables or disables the facility of VBI data insertion during
the Vertical Blanking Interval.
For this purpose Lines 13 to 42 of each frame can be used for VBI
when SMPTE293M standard is used, or Lines 6 to 43 when
ITU-R.BT1358 standard is used
Undershoot Limiter (MR15–MR16)
This control limits the Y signal to a programmable level in the active
video region.
Available limit levels are –1.5 IRE, –6 IRE, –11 IRE.
Note that this facility is only available when Interpolation is enabled
(MR36 = “1”)
Sharpness Filter (MR17)
This control bit enables or disables the Sharpness Filter mode. This
bit must be set to “1” for any values programmed into the Filter
Gain 1 Register to take effect. It must also be set to “1” when
Adaptive Filter mode is used.
Refer to Sharpness Filter control and Adaptive Filter control section.
HATCH
FIELD/FRAME
MR13
100IRE
–40IRE
0IRE
MR12
0
1
TEST PATTERN
ENABLE
MR12
DISABLED
ENABLED
.
MR11
0
1
INPUT FORMAT
MR11
4:4:4 YCRCB
4:2:2 YCRCB
MR10
0
1
PIXEL DATA
ENABLE
MR10
DISABLED
ENABLED
.
–6IRE