ADV7196AKSZ Analog Devices Inc, ADV7196AKSZ Datasheet - Page 5

• Manufacturer Part Number: ADV7196AKSZ
• Manufacturer: Analog Devices Inc

Specifications of ADV7196AKSZ

• Adc/dac Resolution: 11b
• Screening Level: Commercial
• Package Type: MQFP
• Pin Count: 52
• Lead Free Status / RoHS Status: Compliant

3.3 V TIMING–SPECIFICATIONS
P
MPU PORT
ANALOG OUTPUTS
CLOCK CONTROL AND PIXEL PORT
NOTES
1
2
3
Specifications subject to change without notice.
Guaranteed by characterization.
Output delay measured from 50% point of the rising edge of CLOCK to the 50% point of DAC output full-scale transition.
Data: Cb/Cr [9–0], Cr [9–0], Y [9:0]
Control: HSYNC/SYNC, VSYNC/TSYNC, DV
arameter
SCLOCK Frequency
SCLOCK High Pulsewidth, t
SCLOCK Low Pulsewidth, t
Hold Time (Start Condition), t
Setup Time (Start Condition), t
Data Setup Time, t
SDATA, SCLOCK Rise Time, t
SDATA, SCLOCK Fall Time, t
Setup Time (Stop Condition), t
Reset Low Time
Analog Output Delay
Analog Output Skew
f
f
f
Clock High Time t
Clock Low Time t
Data Setup Time t
Data Hold Time t
Control Setup Time t
Control Hold Time t
Pipeline Delay
Pipeline Delay
CLK
CLK
CLK
1
12
10
11
9
5
12
2
11
2
1
3
8
4
7
6
3
Min
0
0.6
1.3
0.6
0.6
100
0.6
100
5.0
5.0
2.0
4.5
7.0
4.0
16
29
(V
T
MIN
AA
= 3.15 V to 3.45 V, V
to T
Typ
10
0.5
1.5
2.0
MAX
(0 C to 70 C) unless otherwise noted.)
Max
400
300
300
27
74.25
81
Unit
kHz
µs
µs
µs
µs
ns
ns
ns
µs
ns
ns
ns
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
Clock Cycles
Clock Cycles
REF
= 1.235 V, R
SET
Conditions
After This Period the 1st Clock Is Generated
Relevant for Repeated Start Condition
Progressive Scan Mode
HDTV Mode
Async Timing Mode and
For 4:4:4 Pixel Input Format at
For 4:4:4 or 4:2:2 Pixel Input Format at
Oversampling
= 2470
, R
LOAD
= 300
1× Interpolation
. All specifications
1× Oversampling
ADV7196A
2×